Apparatus and methods employing a shared read post register file
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael Estlick, Erik Swanson, Eric Dixon, Todd Baumgartner
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Abstract
In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.
Claims21
A processor comprising:
- a plurality of parallel instruction pipes;
- a register file comprising at least one shared register file read port configured to be shared across the plurality of parallel instruction pipes;
- and
- control logic, operatively coupled to the register file, and configured to control the plurality of parallel instruction pipes to read from the at least one shared register file read port,
- and wherein at least one of the plurality of parallel instruction pipes are configured to read from a plurality of non-shared register file read ports of the register file and read from the at least one shared register file read port.
A processor comprising:
- a floating point unit comprising:
- a plurality of parallel instruction pipes;
- a register file comprising a plurality of register file read ports wherein at least two register file read ports are configured to be shared across the plurality of parallel instruction pipes and other register file read ports are configured as non-shared read ports that are dedicated to a respective instruction pipe such that each of at least two instruction pipes is coupled to both at least one non-shared read port and at least one shared read port of the register file;
- and
- control logic, operatively coupled to the register file, and configured to control the at least two instructions pipes to read from respective shared register file read ports and non-shared register file read ports.
A method for instruction execution using a register file comprising:
- receiving one or more multi-source operand instructions for execution;
- and
- controlling execution of the one or more multi-source operand instructions by:
- controlling at least one of a plurality of parallel instruction pipes to read from at least one shared register file read port of a register file and read from non-shared register file read ports of the register file wherein the at least one shared register file read port is also coupled to a parallel instruction pipe different from the plurality of parallel instruction pipes.
A system comprising:
- a first processor;
- and
- a second processor, operatively coupled to the first processor, comprising:
- a plurality of parallel instruction pipes;
- a register file comprising at least one shared register file read port configured to be shared across at least two pipes of the plurality of parallel instruction pipes, wherein at least two pipes of the plurality of parallel instruction pipes are configured to read from a plurality of non-shared register file read ports of the register file and read from the at least one shared register file read port;
- and
- control logic, operatively coupled to the register file, and configured to control the at least two pipes of the parallel instruction pipes to read from the at least one shared register file read port and control at least one of the plurality of parallel instruction pipes to write data for the first processor.
Dependencies are inferred from the claim text.