Multi-table instruction prefetch unit for microprocessor

A processor comprising:

• an instruction fetch unit for fetching instructions, including branch instructions, from an instruction cache for processing in a processor;
• a branch prediction unit for predicting branch instructions;
• and
• an instruction prefetch unit for prefetching instructions into the instruction cache before needed for later execution in the processor, the instruction prefetch unit having at least two different types of branch instruction prefetch tables for storing a branch instruction address identifier and a target address relationship, a first type of branch instruction prefetch table for handling direct uni-target branch instructions and a second type of branch instruction prefetch table for handling indirect multi-target branch instructions,
• wherein the processor is configured to prefetch instructions to the instruction cache before needed for later execution by the processor by:
• sending instructions, including a branch instruction that missed in the instruction cache, to the instruction prefetch unit before needed for later execution by the processor;
• determining whether the branch instruction sent to the instruction prefetch unit that missed in the instruction cache hits in the first type of branch instruction prefetch table or the second type of branch instruction prefetch table;
• reading, in response to the branch instruction hitting in one of the first type of branch instruction prefetch table or the second type of branch instruction prefetch table, a target address from the respective first type of branch instruction prefetch table or the second type of branch instruction prefetch table in which the branch instruction hit;
• and
• prefetching the instruction at the target address for the branch instruction to the instruction cache.