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US 11,960,887 B2Granted
Graphics processing unit and central processing unit cooperative variable length data bit packing
AssigneeIntel Corporation
InventorsBin Wang, Bo Peng
Life of this patent
Estimating the term…
Abstract
Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.
Claims20
A system for packing variable length data comprising:
- a shared memory to store a plurality of sequential pieces of data having variable bit lengths for packing, each piece of data comprising one or more bits including a lead bit, and at least some of the pieces of data having a corresponding bit shift value, each bit shift value to indicate a bit shift for each piece of current data to pack post-shift remainder bits from a piece of prior data before the lead bit of the piece of current data;
- a graphics processing unit (GPU) having access to the shared memory, the GPU to execute, in parallel with individual ones of a plurality of execution units of the GPU, bit shift operations for each piece of current data having a bit shift value, wherein bit shift operations for each piece of current data are executed on a separate individual one of the execution units;
- and
- a central processing unit (CPU) having access to the shared memory, the CPU to provide a first byte of packed variable length data to a CPU accessible memory, the first byte comprising the post-shift remainder bits from the piece of prior data packed with at least the lead bit of the piece of current data.
1 more element
A method for packing variable length data comprising:
- attaining a plurality of sequential pieces of data having variable bit lengths for packing, each piece of data comprising one or more bits including a lead bit;
- determining bit shift values for at least some of the pieces of data, each bit shift value to indicate a bit shift for each piece of current data to pack post-shift remainder bits from a piece of prior data before the lead bit of the piece of current data;
- executing, in parallel with individual ones of a plurality of execution units of a graphics processing unit (GPU), bit shift operations for each piece of current data having a bit shift value, wherein bit shift operations for each piece of current data are executed on a separate individual one of the execution units;
- and
- providing, via a central processing unit (CPU), a first byte of packed variable length data to CPU accessible memory, the first byte comprising the post-shift remainder bits from the piece of prior data packed with at least the lead bit of the piece of current data.
2 more elements
At least one non-transitory machine readable medium comprising a plurality of instructions that, in response to being executed on a computing device, cause the computing device to pack variable length data by:
- attaining a plurality of sequential pieces of data having variable bit lengths for packing, each piece of data comprising one or more bits including a lead bit;
- determining bit shift values for at least some of the pieces of data, each bit shift value to indicate a bit shift for each piece of current data to pack post-shift remainder bits from a piece of prior data before the lead bit of the piece of current data;
- executing, in parallel with individual ones of a plurality of execution units of a graphics processing unit (GPU), bit shift operations for each piece of current data having a bit shift value, wherein bit shift operations for each piece of current data are executed on a separate individual one of the execution units;
- and
- providing, via a central processing unit (CPU), a first byte of packed variable length data, the first byte comprising the post-shift remainder bits from the piece of prior data packed with at least the lead bit of the piece of current data in CPU accessible memory.
2 more elements
Dependencies are inferred from the claim text.