Apparatus and method for complex multiplication

A method comprising:

• decoding a first instruction, the first instruction having a destination operand, a first source operand, and a second source operand;
• wherein the first source operand is to specify a first source register to store a first plurality of packed complex numbers, the second source operand is to specify a second source register to store a second plurality of packed complex numbers, and each of the first plurality and the second plurality of packed complex numbers is composed of a 16-bit half-precision floating-point element in an even position corresponding to a real component and a 16-bit half-precision floating-point element in an odd position corresponding to an imaginary component;
• and
• performing operations corresponding to the first instruction, including, for at least one of the first plurality of packed complex numbers:
• multiplying an element in an even position and an element in an even position of a corresponding one of the second plurality of packed complex numbers to generate a first product,
• multiplying an element in an odd position and an element in an odd position of the corresponding one of the second plurality of packed complex numbers to generate a second product,
• multiplying the element in the odd position and the element in the even position of the corresponding one of the second plurality of packed complex numbers to generate a third product,
• multiplying the element in the even position and the element in the odd position of the corresponding one of the second plurality of packed complex numbers to generate a fourth product,
• subtracting the second product from the first product to generate a first result,
• adding the third product to the fourth product to generate a second result,
• storing the first result in an even position of a corresponding resulting packed complex number in a destination register, and
• storing the second result in an odd position of the corresponding resulting packed complex number in the destination register.

A non-transitory machine-readable medium storing a first instruction having a destination operand, a first source operand, and a second source operand;

• wherein the first source operand is to specify a first source register to store a first plurality of packed complex numbers, the second source operand is to specify a second source register to store a second plurality of packed complex numbers, and each of the first plurality and the second plurality of packed complex numbers is composed of a 16-bit half-precision floating-point element in an even position corresponding to a real component and a 16-bit half-precision floating-point element in an odd position corresponding to an imaginary component, and the first instruction, when executed by a machine, causes the machine to perform a method comprising, for at least one of the first plurality of packed complex numbers:
• multiplying an element in an even position and an element in an even position of a corresponding one of the second plurality of packed complex numbers to generate a first product,
• multiplying an element in an odd position and an element in an odd position of the corresponding one of the second plurality of packed complex numbers to generate a second product,
• multiplying the element in the odd position and the element in the even position of the corresponding one of the second plurality of packed complex numbers to generate a third product,
• multiplying the element in the even position and the element in the odd position of the corresponding one of the second plurality of packed complex numbers to generate a fourth product,
• subtracting the second product from the first product to generate a first result,
• adding the third product to the fourth product to generate a second result,
• storing the first result in an even position of a corresponding resulting packed complex number in a destination register, and
• storing the second result in an odd position of the corresponding resulting packed complex number in the destination register.