Time domain multiply and accumulate system
AssigneeAdvanced Micro Devices, Inc.
InventorsRavinder Reddy Rachala, Stephen Victor Kosonocky, Miguel Rodriguez
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Abstract
A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.
Claims20
A multiply-accumulate circuit comprising:
- a series of ripple counter units comprising:
- a first ripple counter unit comprising a ripple counter having a first input coupled to receive a respective target signal, a second input coupled to receive a respective counter reset value, a third input coupled to receive a respective stop count value, and a counter output;
- a series of additional ripple counter units comprising a ripple counter having a first input coupled to receive a respective target signal, a second input coupled to receive a respective counter reset value, a third input coupled to receive a respective stop count value, and a counter output;
- and an adder circuit coupled to receive the counter output and a sum from a prior adder circuit output in the series of ripple counter units and produce a sum therefrom at an output;
- and
- wherein the ripple counter of each ripple counter unit is controlled by the respective stop count value to adjust a respective ripple counter sampling period with respect to a reference clock signal to scale the respective counter output.
A method of performing a multiply-accumulate computation using digital logic circuits comprising:
- receiving a plurality of target signals at a respective plurality of ripple counters;
- scaling counter outputs of the respective ripple counters by setting stop count values at the respective ripple counters;
- counting pulses of the target signals with respective ones of the plurality of ripple counters to produce respective count values;
- and
- summing the respective count values of the ripple counters.
A processor comprising:
- a processor core;
- a system clock producing a clock signal based on which the processor core operates;
- a multiply-accumulate circuit including a series of ripple counter units comprising:
- a first ripple counter unit comprising a ripple counter having a first input coupled to receive a respective target signal, a second input coupled to receive a respective counter reset value, a third input coupled to receive a respective stop count value, and a counter output;
- a series of additional ripple counter units comprising a ripple counter having a first input coupled to receive a respective target signal from a respective oscillator, a second input coupled to receive a respective counter reset value, a third input coupled to receive a respective stop count value, and a counter output;
- and an adder circuit coupled to receive the counter output and a sum from a prior adder circuit output in the series of ripple counter units and produce a sum therefrom at an output;
- and
- wherein the ripple counters are controlled by the respective stop count values to adjust a respective ripple counter sampling period with respect to a reference clock signal to scale the respective counter outputs.
Dependencies are inferred from the claim text.