Folded integer multiplication for field-programmable gate arrays

An integrated circuit device, comprising:

• programmable logic;
• a multiplier configurable to perform multiplication;
• a first addition/subtraction unit and a second addition/subtraction unit, both configurable to perform addition and subtraction, wherein the integrated circuit device is configurable to determine a plurality of products for a plurality of pairs of input values having a first number of bits, wherein the integrated circuit device is configurable to determine each product of the plurality of products by:
• performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits, wherein the plurality of multiplication operations comprises a first number of multiplication operations and the multiplier is configurable to begin performing each multiplication operation of the plurality of multiplication operations in a first number of consecutive clock cycles equal to the first number of multiplication operations;
• and
• performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction;
• a first set of two registers configurable to receive and store first values generated by the multiplier from performing the plurality of multiplication operations;
• a second set of two registers configurable to receive and store second values generated by the first addition/subtraction unit from performing a first portion of the plurality of operations involving addition or subtraction;
• and
• a third set of registers configurable to receive and store third values generated by the second addition/subtraction unit from performing a second portion of the plurality of operations involving addition or subtraction.

A field-programmable gate array (FPGA) comprising:

• a multiplier configurable to perform multiplication;
• a first addition/subtraction unit and a second addition/subtraction unit, both configurable to perform addition and subtraction;
• a first set of registers configurable to store one or more products generated by the multiplier;
• a second set of registers configurable to store one or more first values generated by the first addition/subtraction unit;
• a third set of registers configurable to store one or more second values generated by the second addition/subtraction unit;
• a first multiplexer communicatively coupled to the multiplier, wherein the first multiplexer is configurable to select a first received value as a first operand to provide to the multiplier based on a first control signal of a plurality of control signals;
• a second multiplexer communicatively coupled to the multiplier, wherein the first multiplexer is configurable to select a second received value as a second operand to provide to the multiplier based on a second control signal of the plurality of control signals;
• and
• control circuitry communicatively coupled to the first and second multiplexers, wherein the control circuitry is configurable to output the plurality of control signals to cause the FPGA to determine a plurality of products for a plurality of pairs of input values having a first number of bits, wherein the FPGA is configurable to determine each product of the plurality of products by:
• performing, using the multiplier and based on the plurality of control signals, a plurality of multiplication operations involving values having fewer bits than the first number of bits, wherein the plurality of multiplication operations comprises a first number of multiplication operations and the multiplier is configurable to begin performing each multiplication operation of the plurality of multiplication operations in a sequence of consecutive clock cycles;
• and
• performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction.