Partitioning in post-layout circuit simulation
AssigneeSynopsys, Inc.
InventorNingjia Zhu
Life of this patent
Estimating the term…
Abstract
New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.
Claims20
A method comprising:
- accessing a first circuit netlist that is related to a reference circuit netlist, wherein the reference circuit netlist is a pre-layout circuit netlist and the first circuit netlist is a post-layout circuit netlist;
- accessing the pre-layout circuit netlist and partitioning the pre-layout circuit netlist into pre-layout sub-circuits;
- accessing the post-layout circuit netlist and partitioning the post-layout circuit netlist into post-layout sub-circuits that correspond to the pre-layout sub-circuits;
- applying first circuit simulations to the pre-layout sub-circuits, the first circuit simulations producing driving information for some of the pre-layout subcircuits;
- and
- applying, by a processing device, second circuit simulations to the post-layout sub-circuits, wherein the driving information produced by the first circuit simulations of the pre-layout sub-circuits provide stimulus for inputs to the second circuit simulations of the post-layout sub-circuits.
A system comprising:
- a database storing, in a shared format, both a pre-layout circuit netlist partitioned into pre-layout sub-circuits, and a post-layout circuit netlist partitioned into post-layout sub-circuits that correspond to the pre-layout sub-circuits;
- a memory storing instructions and a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- access both the pre-layout sub-circuits and the corresponding post-layout sub-circuits from the shared database;
- and
- apply first circuit simulations to the pre-layout sub-circuits, the first circuit simulations producing driving information for some of the pre-layout subcircuits;
- and
- apply second circuit simulations to the post-layout sub-circuits, wherein the driving information produced by the first circuit simulations of the pre-layout sub-circuits provide stimulus for inputs to the second circuit simulations of the post-layout sub-circuits.
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
- access a first circuit netlist that is related to a reference circuit netlist, wherein the reference circuit netlist is a pre-layout circuit netlist and the first circuit netlist is a post-layout circuit netlist;
- access the pre-layout circuit netlist and partition the pre-layout circuit netlist into pre-layout sub-circuits;
- access the post-layout circuit netlist and partition the post-layout circuit netlist into post-layout sub-circuits that correspond to the pre-layout sub-circuits;
- apply first circuit simulations to the pre-layout sub-circuits, the first circuit simulations producing driving information for some of the pre-layout subcircuits;
- and
- apply second circuit simulations to the post-layout sub-circuits, wherein the driving information produced by the first circuit simulations of the pre-layout sub-circuits provide stimulus for inputs to the second circuit simulations of the post-layout sub-circuits.
Dependencies are inferred from the claim text.