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US 11,960,776 B2Granted
Data protection for stacks of memory dice
AssigneeMicron Technology, Inc.
InventorsMarco Sforzin, Paolo Amato
Life of this patent
Estimating the term…
Abstract
Some memory dice in a stack can be connected externally to the stack and other memory dice in the stack can be connected internally to the stack. The memory dice that are connected externally can act as interface dice for other memory dice that are connected internally thereto. Data protection and recovery schemes provided for the stacks of memory dice can be based on data that are transferred in a single data stream without a discontinuity between those data transfers from the memory dice of the stacks.
Claims20
An apparatus, comprising:
- a first number of memory units configured for host data, each memory unit of the first number of memory units further comprising:
- a primary memory die configured for a respective first portion of the host data and coupled to a respective first substrate via a respective first external data link;
- and
- a secondary memory die configured for a respective second portion of the host data and coupled to the primary memory die via a respective first internal data link;
- and
- a second memory unit configured for parity data to perform an error correction operation on the host data, the second memory unit further comprising:
- a primary memory die configured for a respective first portion of the parity data and coupled to a respective second substrate via a respective second external data link;
- and
- a secondary memory die configured for a respective second portion of the parity data and coupled to the primary memory die via a respective second internal data link.
6 more elements
A method, comprising:
- during a first portion of a burst length:
- sending a signal indicative of first host data from a respective primary memory die of each memory unit of a first number of memory units via a first external data link;
- and
- sending a signal indicative of first parity data for performing an error correction operation on the first host data from a primary memory die of a second memory unit via a second external data link;
- and
- during a second portion of the burst length:
- sending a signal indicative of second host data from a secondary memory die of each memory unit of the first number of memory units via the first external data link;
- and
- sending a signal indicative of second parity data for performing the error correction operation on the second host data from a secondary memory die of the second memory unit via the second external data link.
6 more elements
A method, comprising:
- during a first portion of a burst length:
- receiving signals indicative of a first number of data symbols from respective primary memory dice of a first number of memory units via respective first external links;
- and
- receiving signals indicative of a first number of parity symbols from a primary die of a second memory unit via a second external link;
- during a second portion of the burst length:
- receiving signals indicative of a second number of data symbols from respective secondary memory dice of the first number of memory units via the respective first external links;
- and
- receiving signals indicative of a second number of parity symbols from the secondary memory die of the second memory unit via the second external link;
- and
- performing an error correction operation on a codeword comprising the first and the second number of data symbols and the first and the second number of parity symbols using the first and the second number of parity symbols to correct one or more symbol errors in the codeword.
7 more elements
Dependencies are inferred from the claim text.