Memory dice internal clock
AssigneeMicron Technology, Inc.
InventorsLiang Yu, Luigi Pilolli, Biagio Iorio
Life of this patent
Estimating the term…
Abstract
A method includes selecting a particular ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B # pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.
Claims20
A method, comprising:
- selecting a primary ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device;
- setting the primary R/B # pin to low status;
- receiving, by at least one memory die among the plurality of memory dice, signaling indicative of performance of a memory access for the primary R/B # pin;
- receiving, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a first memory die among the plurality of memory dice;
- receiving, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a second memory die among the plurality of memory dice;
- initiating a first internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the first memory die among the plurality of memory dice;
- and
- initiating a second internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the second memory die among the plurality of memory dice, wherein the first internal clocking signal and the second internal clocking signal are associated with timing of operations performed by the plurality of memory dice.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
- select a primary ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device;
- set the primary R/B # pin to low status;
- receive, by at least one memory die among the plurality of memory dice, signaling indicative of performance of memory access for the primary R/B # pin;
- receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a first memory die among the plurality of memory dice;
- receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a second memory die among the plurality of memory dice;
- initiate a first internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the first memory die among the plurality of memory dice;
- and
- initiate a second internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the second memory die among the plurality of memory dice.
A system, comprising:
- a plurality of memory components that share a peak power characteristic, wherein each memory component is associated with a ready/busy pin (R/B #) among a plurality of R/B # pins;
- and
- a processor operatively coupled to the plurality of memory components, to:
- select a particular R/B # pin from the plurality of R/B # pins to have a singular status for the plurality of memory components;
- receive, by at least one memory die among a plurality of memory dice, signaling indicative of performance of a memory access of a first memory component of the plurality of memory components;
- receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access of a second memory component of the plurality of memory components responsive to signaling indicative of completion of the performance of the memory access of the first memory component of the plurality of memory components;
- and
- initiate an internal clocking signal subsequent to receipt of the signaling indicative of completion of performance of the memory access of a last memory component of the plurality of memory components.
Dependencies are inferred from the claim text.