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US 11,960,744 B2Granted
Register operation in memory devices
AssigneeMicron Technology, Inc.
InventorHari Giduturi
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a memory partition. The semiconductor device further includes a plurality of registers. A first register of the plurality of registers, when in operation, controls an operation associated with the memory partition. The semiconductor device additionally includes a memory controller. When in operation, the memory controller accesses a first location of the memory partition concurrently with accessing the first register.
Claims21
A device, comprising:
- a memory partition;
- a plurality of registers, wherein a first register of the plurality of registers when in operation stores a value associated with one of a first configuration setting of a memory device comprising the memory partition, a second configuration setting of a component of the memory device, a first status of the memory device, a second status of the component of the memory device, a first parameter of the memory device, or a second parameter of the component of the memory device, or a predetermined pattern;
- and
- a memory controller that when in operation accesses a first location of the memory partition concurrently with accessing the first register, wherein concurrently accessing the first register comprises initiating access of the first register at a predetermined time during a latency period associated with the access of the first location of the memory partition, wherein the latency period comprises a period of time to access the first location of the memory partition, wherein the predetermined time is selected to allow for completion of the access of the first register during the latency period.
1 more element
A device, comprising:
- a memory controller that when in operation:
- initiates an access of a first portion of a memory partition at a predetermined first time;
- initiates an access of a register at a predetermined second time during a latency period associated with access of the first portion of the memory partition, wherein the latency period comprises a time period in which to access the first portion of the memory partition, wherein the second predetermined time is selected to allow for completion of the access of first register during the latency period;
- and
- initiates an access of a second portion of the memory partition at a predetermined third time occurring during the access of the first portion of the memory partition or subsequent to completion of the access of the first portion of the memory partition or initiates a access of a second memory partition at the predetermined third time.
2 more elements
A method, comprising:
- initiating a memory access of a memory device via a memory controller;
- initiating, via the memory controller, a register access of the memory device concurrently with the memory access of the memory device by initiating access of the register at a predetermined time during a latency period associated with the memory access of the memory device, wherein the latency period comprises a period of time to access the memory device, wherein the predetermined time is selected to allow for completion of the access of the register during the latency period;
- completing the memory access of the memory device;
- and
- initiating a second memory access of the memory device via the memory controller subsequent to completion of the memory access of the memory device.
2 more elements
Dependencies are inferred from the claim text.