Logic fabric based on microsector infrastructure with data register having scan registers
AssigneeIntel Corporation
InventorsSean R Atsatt, Ilya K. Ganusov
Life of this patent
Estimating the term…
Abstract
Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
Claims20
An integrated circuit, comprising:
- a first microsector, comprising:
- memory configured to store first data and second data;
- a data register configured to write the first data to the memory;
- a first shift register configured to receive the second data from the memory, wherein the second data bypasses the data register in transmission to the first shift register;
- and
- a row controller coupled to the first microsector, wherein the row controller receives the second data in response to transmitting a control signal to the first shift register to instruct a read of the second data.
A method, comprising:
- receiving a data packet from a data path;
- generating, using a finite state machine, a plurality of control signals to read stored data from a register of a microsector at least in part by a shifting the read stored data from the register to a buffer using a quasi-delay insensitive (QDI) shift register in response to the data packet, wherein the QDI shift register receives a read data bit from the register and an in use bit from configuration memory;
- inserting the read stored data to add one or more bits to one or more slots of the data packet;
- and
- transmitting the data packet comprising the read stored data to the data path.
A system, comprising:
- programmable logic comprising a plurality of configuration memory and a register;
- and
- control circuitry disposed between portions of the programmable logic and on a same board, wherein the control circuitry is configured to:
- receive a data packet from a data path;
- and
- generate, using a finite state machine, a plurality of control signals to read stored data from the register of a microsector at least in part by a shifting the read stored data from the register to a buffer using a quasi-delay insensitive (QDI) shift register in response to the data packet, wherein the QDI shift register is configured to transmit the read stored data based at least in part on handshaking operations.
Dependencies are inferred from the claim text.