Back to results
US 11,960,731 B2Granted
FIFO memory error condition detection
AssigneeMicron Technology, Inc.
InventorLance P. Johnson
Life of this patent
Estimating the term…
Abstract
An apparatus can include first circuitry coupled to a FIFO memory. The first circuitry can provide a write pointer of the FIFO memory at a first rate. Second circuitry can be coupled to the FIFO memory. The second circuitry can provide a read pointer of the FIFO memory at a second rate that is different from the first rate. Third circuitry can be coupled to the first and second circuitries. The third circuitry can provide an indication of an error condition of the FIFO memory based on the write pointer and the read pointer.
Claims23
An apparatus, comprising:
- a first in first out (FIFO) memory;
- first circuitry coupled to the FIFO memory and configured to provide a write pointer of the FIFO memory;
- second circuitry coupled to the FIFO memory and configured to provide a read pointer of the FIFO memory;
- and
- third circuitry coupled to the first and second circuitries and configured to:
- provide a first signaling indicative of whether a first value of the write pointer for a current cycle of a read clock is a first particular value;
- perform a first logical operation on the first signaling and second signaling indicative of the read pointer,
- wherein a result of the first logical operation is indicative of a potential error condition being overflow of the FIFO memory;
- provide a third signaling indicative of whether a second value of the write pointer for a subsequent cycle of the read clock is a second particular value;
- and
- perform a second logical operation on the third signaling and the second signaling,
- wherein a result of the second logical operation is indicative of the potential error condition being underflow of the FIFO memory.
9 more elements
A method, comprising:
- performing, by interface (I/F) circuitry of a memory system comprising a first in first out (FIFO) memory, a first logical operation on first signaling and second signaling,
- wherein the first signaling is indicative of a first value of a write pointer of the FIFO memory corresponding to a current cycle of a read clock of the memory system, and
- wherein the second signaling is indicative of a read pointer of the FIFO memory corresponding to the current cycle of the read clock of the memory system;
- performing, by the I/F circuitry, a second logical operation on the second and third signaling,
- wherein the third signaling is indicative of a second value of the write pointer corresponding to a subsequent cycle of the read clock;
- responsive to the first logical operation yielding a first particular result, providing, by the I/F circuitry, fourth signaling indicative of a potential overflow of the FIFO memory;
- and
- responsive to the second logical operation yielding a second particular result, providing, by the I/F circuitry, fifth signaling indicative of a potential underflow of the FIFO memory.
5 more elements
An apparatus, comprising:
- a first in first out (FIFO) memory;
- and
- control circuitry coupled to the FIFO memory and configured to:
- generate a write pointer for the FIFO memory according to one-hot encoding;
- generate a read pointer for the FIFO memory according to binary encoding and a clock;
- detect a potential overflow of the FIFO memory based on a first value of the write pointer corresponding to a current cycle of the clock and a value of the read pointer;
- and
- detect a potential underflow of the FIFO memory based on a second value of the write pointer corresponding to a subsequent cycle of the clock and the value of the read pointer.
5 more elements
A non-transitory medium storing instructions executable by a processing device to:
- monitor an output of first logical operation circuitry having current values of a read pointer of a first in first out (FIFO) memory and current values of a write pointer of the FIFO memory as inputs,
- wherein a change in the output of the first logical operation circuitry is indicative of a potential overflow of the FIFO memory;
- and
- monitor an output of second logical operation circuitry having directly subsequent values of the write pointer and the current values of the read pointer as inputs,
- wherein a change in the output of the second logical operation circuitry is indicative of a potential underflow of the FIFO memory.
2 more elements
Dependencies are inferred from the claim text.