NVMe controller memory manager providing CMB capability
AssigneeWestern Digital Technologies, Inc.
InventorShay Benisty
Life of this patent
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Abstract
Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.
Claims20
A method of accessing non-volatile memory express (NVMe) queues to access a storage device, comprising:
- storing a NVMe queue in a dynamic random access memory (DRAM) of the storage device;
- utilizing a static random access memory (SRAM) of the storage device as a cache to the NVMe queue;
- receiving a plurality of host commands;
- storing the host commands to the SRAM;
- aggregating the host commands to a full DRAM cache line size;
- and
- flushing the full DRAM cache line size host commands from the SRAM to a tail of a submission queue of the NVMe queue.
A method of accessing non-volatile memory express (NVMe) queues to access a storage device, comprising:
- storing a NVMe queue in a dynamic random access memory (DRAM) of the storage device;
- utilizing a static random access memory (SRAM) of the storage device as a cache to the NVMe queue;
- fetching two DRAM cache lines of a head of a submission queue of the NVMe queue;
- and
- storing the fetched two DRAM cache lines to the SRAM.
A method of accessing non-volatile memory express (NVMe) queues to access a storage device, comprising:
- storing a NVMe queue in a dynamic random access memory (DRAM) of the storage device;
- utilizing a static random access memory (SRAM) of the storage device as a cache to the NVMe queue;
- storing a plurality of completion commands to the SRAM;
- aggregating the completion commands to two full DRAM cache line sizes;
- and
- flushing the two full DRAM cache line sizes completion commands from the SRAM to a tail of a completion queue of the NVMe queue.
A method of accessing non-volatile memory express (NVMe) queues to access a storage device, comprising:
- storing a NVMe queue in a dynamic random access memory (DRAM) of the storage device;
- utilizing a static random access memory (SRAM) of the storage device as a cache to the NVMe queue;
- fetching one DRAM cache line of a head of a completion queue of the NVMe queue;
- and
- storing the fetched one DRAM cache line to the SRAM.
A method of accessing non-volatile memory express (NVMe) queues to access a storage device, comprising:
- storing a NVMe queue in a dynamic random access memory (DRAM) of the storage device, wherein the storage device comprises a controller memory buffer (CMB)/persistent memory region (PMR) manager, wherein the CMB/PMR manager comprises a transaction classifier and cache tables;
- and
- utilizing a static random access memory (SRAM) of the storage device as a cache to the NVMe queue.
A method of accessing a storage device, comprising:
- a step for receiving host write transactions;
- a step for classifying the host write transactions into a non-volatile memory express (NVMe) data structure group;
- and
- a step for storing the NVMe data structure groups within non-volatile memory (NVM) and volatile memory.
Dependencies are inferred from the claim text.