Fast secure booting method and system

A secure booting circuit for verification of initiation of a boot sequence for an electronic device, comprising:

• a move engine configured to read verification data from a non-volatile memory circuit storing memory content and an error correction code corresponding to the memory content, the verification data is determined based on verification data configuration and including the error correction code and not including all of the memory content;
• an interface component with an input connected to a secure memory and configured to read a reference data from the secure memory, the reference data including encrypted expected error correction code, an expected erase/write count, and an expected selective subset of the memory content;
• an encryption module coupled to the move engine and configured to receive the verification data from the move engine and encrypt the verification data to generate a digest;
• and
• a verification circuit coupled to the encryption module and the interface component and configured to verify the digest based on the reference data and to provide a verification signal indicating whether the boot sequence passes the verification.

A secure booting system for verification of initiation of a boot sequence for an electronic device, comprising:

• a non-volatile memory circuit including a non-volatile memory and a memory controller, wherein the non-volatile memory is configured to store a memory content associated with the boot sequence and wherein the memory controller is configured to calculate an error correction code based on the memory content stored in the non-volatile memory;
• a secure boot circuit coupled to the non-volatile memory circuit via a first transfer bus;
• and
• a secure memory coupled to the secure boot circuit via a second transfer bus, wherein the secure memory is configured to store reference data including an expected error correction code, an expected erase/write count, and an expected selective subset of the memory content;
• wherein the secure boot circuit is configured to provide a verification signal by comparing verification data with the reference data, without hashing all of the memory content stored in the non-volatile memory, wherein the verification data is determined based on verification data configuration and includes at least the error correction code, and wherein the boot sequence is initiated in a normal mode if the verification signal is in a first state and the boot sequence is not initiated in the normal mode if the verification signal is in a second state.