Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture
AssigneeRambus Inc.
InventorsSteven C. Woo, Michael Raymond Miller
Life of this patent
Estimating the term…
Loading patent…
AssigneeRambus Inc.
InventorsSteven C. Woo, Michael Raymond Miller
Estimating the term…
A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.
An integrated circuit (IC) device comprising:
A method of streaming operands from a memory die into a series of processing elements, each processing element having local processing-element storage, the method comprising:
A method of streaming operands from a memory die into a series of processing elements, each processing element having local processing-element storage, the method comprising:
Dependencies are inferred from the claim text.