PCIe controller and loopback data path using PCIe controller

A method for updating a data key, comprising:

• receiving a key update command;
• generating an outgoing DMA command according to the key update command;
• decrypting a cipher text data by using a first key to obtain a plaintext data;
• caching the plaintext data in a solid-state storage device through a loopback path;
• in response to a completion of an outgoing DMA command processing, generating a receiving DMA command;
• encrypting the plaintext data cached by using a second key;
• and
• writing the encrypted data into the solid-state storage device.

A method for processing a key update command, comprising:

• in response to a key update command, reading data from a logical address instructed by the key update command, and storing the data read at a first address of a cache;
• initiating an outgoing DMA transmission to move the data from the first address to a second address, and during the transfer process, decrypting the data read by using an old key to obtain a plaintext data and encrypting the plaintext data by using a new key to obtain a cipher text data;
• and
• writing the cipher text data at the second address into the logical address;
• wherein an outgoing DMA module sends the plaintext data to a transport layer transmission module;
• the transport layer transmission module sends the plaintext data to a second loopback control module via a first loopback control module according to the destination address of the DMA transmission;
• a transport layer reception module provides the plaintext data received by the second loopback control module to a memory access module;
• and the memory access module stores the cipher text data in the second address of the cache.

A PCIe controller, comprising a transport layer transmission module, a transport layer reception module, a memory access module, an outgoing DMA module, a receiving DMA module, an encryption module, a decryption module, and a memory;

• wherein the transport layer transmission module comprises a first loopback control module, the transport layer reception module comprises a second loopback control module, and the first loopback control module is coupled to the second loopback control module;
• the memory access module is coupled to the transport layer transmission module and the transport layer reception module, and the memory access module is further coupled to the memory;
• the outgoing DMA module is coupled to the decryption module, and the outgoing DMA module is also coupled to the transport layer transmission module;
• the receiving DMA module is coupled to the encryption module, and the receiving DMA module is also coupled to the transport layer reception module;
• and the encryption module and the decryption module are also coupled to DRAM outside the PCIe controller, separately,
• wherein
• the decryption module is configured to decrypt the data obtained from the DRAM, and provide the decrypted data to the outgoing DMA module,
• the first loopback control module sends parts of TLPs to the second loopback control module,
• the first loopback control module sends the TLPs with the specified identifier and/or the TLPs accessing the specified address space to the second loopback control module, and
• the second loopback control module sends the TLP received by the first loopback control module to the memory access module or the receiving DMA module.