Semiconductor memory systems with on-die data buffering

A dynamic random access memory (DRAM) chip package, comprising:

• multiple DRAM integrated circuit (IC) chips, a first one of the multiple DRAM IC chips comprising
• an array of DRAM storage cells;
• a primary data interface, in a first mode of operation, to receive a serialized write data stream from a first integrated circuit (IC) chip, the primary interface to deserialize the serialized write data stream into a first plurality of data streams;
• and
• a secondary data interface, in the first mode of operation, to transmit the first plurality of data streams to a second one of the multiple DRAM IC chips during an interval associated with write operations.

A method of operation in a dynamic random access memory (DRAM) integrated circuit (IC) chip, the DRAM IC chip including an array of DRAM storage cells, the method comprising:

• in a first mode of operation
• receiving a serialized write data stream with a primary data interface, the serialized write data stream received from a first integrated circuit (IC) chip during an interval associated with write operations;
• deserializing, with the primary data interface, the serialized write data stream into a first plurality of data streams;
• and
• transmitting the first plurality of data streams to a second DRAM IC chip.