Semiconductor memory device including unit page buffer blocks having four page buffer pairs

A semiconductor memory device comprising:

• a unit page buffer block including four page buffer pairs arranged in a column direction,
• wherein each of the four page buffer pairs comprises:
• a common column decoder block;
• and
• an upper page buffer stage and a lower page buffer stage, each electrically and commonly connected to the common column decoder block,
• wherein the upper buffer stage comprises:
• an upper selection block;
• an upper latch block;
• and
• an upper cache block,
• wherein the lower buffer stage comprises:
• a lower selection block;
• a lower latch block;
• and
• a lower cache block,
• wherein:
• the upper selection block includes a plurality of upper sub-selection blocks arranged in a row direction, and each of the plurality of upper sub-selection blocks includes a plurality of upper unit selection blocks,
• the upper latch block includes a plurality of upper sub-latch blocks arranged in the row direction,
• the upper cache block includes a plurality of upper sub-cache blocks arranged in the row direction,
• each of the plurality of upper unit selection blocks, each of the plurality of upper sub-latch blocks, and each of the plurality of upper sub-cache blocks are electrically connected to each other,
• the lower selection block includes a plurality of lower sub-selection blocks arranged in the row direction, and each of the plurality of lower sub-selection blocks includes a plurality of lower unit selection blocks,
• the lower latch block includes a plurality of lower sub-latch blocks arranged in the row direction,
• the lower cache block includes a plurality of lower sub-cache blocks arranged in the row direction, and
• each of the plurality of lower unit selection blocks, the plurality of lower sub-latch blocks, and each of the lower sub-cache blocks are electrically connected to each other.

A semiconductor memory device comprising:

• a unit page buffer block including first to fourth page buffer pairs arranged in a column direction,
• wherein each of the first to fourth page buffer pairs comprises:
• a common column decoder block;
• and
• an upper page buffer stage and a lower page buffer stage electrically connected to a corresponding common column decoder block,
• wherein the common column decoder block includes first and second sub-common column decoder blocks,
• wherein the upper page buffer stage comprises:
• an upper selection block;
• an upper latch block;
• and
• an upper cache block,
• wherein the lower page buffer stage comprises:
• a lower selection block;
• a lower latch block;
• and
• a lower cache block,
• wherein:
• the upper selection block includes a first upper unit selection block and a second upper unit selection block arranged in the column direction;
• the upper latch block includes first and second upper sub-latch blocks arranged in the row direction,
• the upper cache block includes first and second upper sub-cache blocks arranged in the row direction,
• the lower selection block includes a first upper unit selection block and a first lower unit selection block arranged in the column direction,
• the lower latch block includes first and second lower sub-latch blocks arranged in the row direction,
• the lower cache block includes first and second lower sub-cache blocks arranged in the row direction,
• the first upper unit selection block, the first upper sub-latch block, and the first upper sub-cache block are electrically connected to each other,
• the second upper unit selection block, the second upper sub-latch block, and the second upper sub-cache block are electrically connected to each other,
• the first lower unit selection block, the first lower sub-latch block, and the first lower sub-cache block are electrically connected to each other,
• the second lower unit selection block, the second lower sub-latch block, and the second lower sub-cache block are electrically connected to each other,
• the first upper sub-cache block and the first lower sub-cache block are commonly electrically connected to the first sub-common column decoder, and
• the second upper sub-cache block and the second lower sub-cache block are commonly electrically connected to the second sub-common column decoder block.