US 11,960,404 B2 · Method and apparatus for reducing the latency of long latency memory requests

Abstract

Systems, apparatuses, and methods for efficiently processing memory requests are disclosed. A computing system includes at least one processing unit coupled to a memory. Circuitry in the processing unit determines a memory request becomes a long-latency request based on detecting a translation lookaside buffer (TLB) miss, a branch misprediction, a memory dependence misprediction, or a precise exception has occurred. The circuitry marks the memory request as a long-latency request such as storing an indication of a long-latency request in an instruction tag of the memory request. The circuitry uses weighted criteria for scheduling out-of-order issue and servicing of memory requests. However, the indication of a long-latency request is not combined with other criteria in a weighted sum. Rather, the indication of the long-latency request is a separate value. The circuitry prioritizes memory requests marked as long-latency requests over memory requests not marked as long-latency requests.

Claims20

Dependent claims

An apparatus comprising:

a queue comprising a first memory request with a first priority and a second memory request with a second priority higher than the first priority;
and
circuitry configured to:
store an indication that the first memory request is a long-latency request, based at least in part on execution of the first memory request causing a page table walk;
and
cause the first memory request to issue prior to the second memory request, responsive to the indication that the first memory request is a long-latency request.

3 more elements

Dependencies are inferred from the claim text.

Method and apparatus for reducing the latency of long latency memory requests

Life of this patent

Method and apparatus for reducing the latency of long latency memory requests

Life of this patent

Abstract

Claims20