Integrated circuit and configuration method thereof
AssigneeSigmastar Technology Ltd.
InventorXiaolong Liu
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Abstract
An integrated circuit and a configuration method thereof are disclosed. The integrated circuit, applied to a neural network model calculation, includes a first operator engine, a second operator engine, a random access memory (RAM) and a direct memory access (DMA) engine. The first operator engine is configured to perform a first calculation operation. The second operator engine is configured to perform a second calculation operation. The DMA engine performs an access operation on the RAM according to a first memory management unit (MMU) table when the first operator engine performs the first calculation operation, and performs an access operation on the RAM according to a second MMU table when the second operator engine performs the second calculation operation.
Claims12
An integrated circuit, applied to a neural network model calculation, comprising:
- a first operator engine, configured to perform a first calculation operation;
- a second operator engine, configured to perform a second calculation operation;
- a random access memory (RAM);
- and
- a direct memory access (DMA) engine, configured to perform an access operation on the RAM according to a first memory management unit (MMU) table when the first operator engine performs the first calculation operation, and to perform an access operation on the RAM according to a second MMU table when the second operator engine performs the second calculation operation.
A configuration method of an integrated circuit, comprising:
- partitioning tensor memories needed for a calculation of a neural network model into to a plurality of corresponding predetermined unit pages;
- performing data dependency analysis individually on the plurality of predetermined unit pages to establish a plurality of data dependencies, and allocating a plurality of virtual buffers to the plurality of predetermined unit pages according to the plurality of data dependencies;
- performing life cycle analysis individually on the plurality of virtual buffers, wherein an analysis result of the life cycle analysis indicates respective life cycles of the plurality of virtual buffers;
- allocating a plurality of physical buffers according to the analysis result;
- and
- establishing a plurality of predetermined memory management unit (MMU) tables to record mapping relationships between virtual addresses and physical addresses, so as to allow the integrated circuit to look up at least one physical address for data access according to at least one mapping relationship in a pre-loaded MMU table in a utilization stage, wherein the pre-loaded MMU table is selected from the plurality of predetermined MMU tables.
Dependencies are inferred from the claim text.