Managing multiple cache memory circuit operations
AssigneeCadence Design Systems, Inc.
InventorsRobert T. Golla, Matthew B. Smittle
Life of this patent
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AssigneeCadence Design Systems, Inc.
InventorsRobert T. Golla, Matthew B. Smittle
Estimating the term…
A cache memory circuit capable of dealing with multiple conflicting requests to a given cache line is disclosed. In response to receiving an acquire request for the given cache line from a particular lower-level cache memory circuit, the cache memory circuit sends probe requests regarding the given cache line to other lower-level cache memory circuits. In situations where a different lower-level cache memory circuit is simultaneously trying to evict the given cache line at the particular lower-level cache memory circuit is trying to obtain a copy of the cache line, the cache memory circuit performs a series of operations to service both requests and ensure that the particular lower-level cache memory circuit receives a copy of the given cache line that includes any changes in the evicted copy of the given cache line.
An apparatus, comprising:
A method, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.