Relaxed invalidation for cache coherence

A processing system, comprising:

• a plurality of processing cores;
• and
• a plurality of private caches, each private cache associated with a corresponding processing core of the plurality of processing cores;
• wherein the processing system is configured to:
• generate one or more notifications of a write operation associated with a first private cache of the plurality of private caches responsive to the write operation, the first private cache associated with one processing core of the plurality of processing cores;
• delay transmission of the one or more notifications of the write operation to any private cache of the plurality of private caches until a synchronization event occurs;
• and
• responsive to the synchronization event, provide the one or more notifications at least one of the private caches.

A shared cache communicatively coupled to a plurality of processing cores and to a plurality of private caches each associated with a corresponding processing core of the plurality of processing cores, the shared cache configured to:

• generate one or more notifications of a write operation associated with a first private cache of the plurality of private caches responsive to the write operation, the first private cache associated with a first processing core of the plurality of processing cores;
• delay transmission of the one or more notifications of the write operation to any private cache of the plurality of private caches until a synchronization event occurs;
• and
• provide, responsive to the synchronization event, the one or more notifications to at least one of the private caches.