Enhanced data reliability in multi-level memory cells
AssigneeMicron Technology, Inc.
InventorsDeping He, David Aaron Palmer
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorsDeping He, David Aaron Palmer
Estimating the term…
Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.
A non-transitory computer-readable medium storing code comprising instructions executable by one or more processors to:
A memory system, comprising:
Dependencies are inferred from the claim text.