Automatic generation of integrated test procedures using system test procedures

A system for automatic generation of integrated test procedures using system test procedures, the system comprising:

• a processor circuit;
• and
• a memory associated with the processor circuit, the memory comprising computer readable program instructions that, when executed by the processor circuit cause the system to perform operations comprising:
• generating, by a processor circuit, a system test procedure test case for each system model of a plurality of system models;
• automatically generating, by the processor circuit, an integrated test procedure test harness comprising a group of interacting system models of the plurality of system models, an output signal from one or more of the interacting system models being an input signal to one or more other interacting system models;
• automatically generating, by the processor circuit, an integrated test procedure test case using the system test procedure test case for each system model in the integrated test procedure test harness;
• automatically running, by the processor circuit, the integrated test procedure test case;
• analyzing a correlation between one or more inputs and one or more outputs of the integrated test procedure test case to determine a group of critical inputs, the group of critical inputs being the inputs that are needed to affect each output of the integrated test procedure test case;
• and
• generating, by the processor circuit, an integrated test procedure coverage report in response to running the integrated test procedure test case.

A non-transitory computer readable medium including instructions storied therein that are executable by a processing circuit to perform operations comprising:

• generating, by a processor circuit, a system test procedure test case for each system model of a plurality of system models;
• automatically generating, by the processor circuit, an integrated test procedure test harness comprising a group of interacting system models of the plurality of system models, an output signal from one or more of the interacting system models being an input signal to one or more other interacting system models;
• automatically generating, by the processor circuit, an integrated test procedure test case using the system test procedure test case for each system model in the integrated test procedure test harness;
• automatically running, by the processor circuit, the integrated test procedure test case;
• analyzing a correlation between one or more inputs and one or more outputs of the integrated test procedure test case to determine a group of critical inputs, the group of critical inputs being the inputs that are needed to affect each output of the integrated test procedure test case;
• and
• generating, by the processor circuit, an integrated test procedure coverage report in response to running the integrated test procedure test case.