Redundancy-based error detection in a memory device
AssigneeMicron Technology, Inc.
InventorsScott E. Schaefer, Aaron P. Boehm
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Abstract
Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.
Claims25
A method, comprising:
- reading, from memory, a first codeword comprising a first set of data bits representative of a set of data and a second codeword comprising a second set of data bits representative of the set of data;
- generating, based at least in part on reading the first codeword from the memory, an error detection bit that indicates whether an error has been detected in the first codeword;
- generating, based at least in part on reading the first codeword and the second codeword from the memory, a match bit that indicates whether a portion of the first codeword matches a corresponding portion of the second codeword;
- and
- determining an error status of the first codeword based at least in part on the match bit and the error detection bit.
A method, comprising:
- transmitting a read command for a set of data that is associated with a first codeword and a second codeword, wherein the first codeword comprises a first set of data bits representative of the set of data, and wherein the second codeword comprises a second set of data bits representative of the set of data;
- determining, based at least in part on transmitting the read command, a match bit that indicates whether a portion of the first codeword matches a corresponding portion of the second codeword, and an error detection bit that indicates whether a memory device detected an error in the first codeword;
- and
- determining an error status of the first codeword based at least in part on the match bit and the error detection bit.
A memory system, comprising:
- one or more memories;
- and
- one or more controllers coupled with the one or more memories and configured to cause the memory system to:
- read, from the one or more memories, a first codeword comprising a first set of data bits representative of a set of data and a second codeword comprising a second set of data bits representative of the set of data;
- generate, based at least in part on reading the first codeword from the one or more memories, an error detection bit that indicates whether an error has been detected in the first codeword;
- generate, based at least in part on reading the first codeword and the second codeword from the one or more memories, a match bit that indicates whether a portion of the first codeword matches a corresponding portion of the second codeword;
- and
- determine an error status of the first codeword based at least in part on the match bit and the error detection bit.
Dependencies are inferred from the claim text.