Memory controller with looped-back calibration data receiver

A method of operation within a memory control component having first and second signaling contacts coupled respectively to counterpart signaling contacts of a memory IC, the method comprising:

• transmitting a write data signal to the memory IC via the first signaling contact while operating in an active mode, the write data signal conveying a plurality of data values to be stored within a memory core of the memory IC;
• and
• while operating in a calibration mode:
• transmitting, via the first signaling contact, a timing calibration signal to be sampled by the memory IC;
• and
• receiving, via the second signaling contact, a plurality of digital samples of the timing calibration signal generated by the memory IC.

A memory control component comprising:

• a data signaling interface to transmit:
• (i) data to an integrated-circuit memory device via a data link during active-mode operation of the memory control component, the data to be stored within a core storage array of the integrated-circuit memory device, and
• (ii) a timing calibration pattern to the integrated-circuit memory device via the data link during a calibration-mode operation of the memory control component, the timing calibration pattern to be sampled within the memory device to generate calibration pattern samples that are transmitted to the memory control component via a calibration signaling link without storage within the core storage array;
• and
• a calibration signaling interface dedicated to receiving the calibration pattern samples transmitted via the calibration signaling link.