Power delivery reduction scheme for SoC
AssigneeApple Inc.
InventorsJamie L. Langlinais, Inder M. Sodhi, Lior Zimet, Keith Cox
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AssigneeApple Inc.
InventorsJamie L. Langlinais, Inder M. Sodhi, Lior Zimet, Keith Cox
Estimating the term…
Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.
A system comprising:
A method comprising:
A non-transitory computer readable medium storing a plurality of instructions for a power management processor in a power management circuit of an integrated circuit that also comprises a plurality of components, wherein the integrated circuit further comprises a global power control circuit configured to apply power control across the plurality of components responsive to trigger signals to the integrated circuit, and wherein the plurality of instructions, when executed by the power management processor, cause the power management processor to perform operations comprising;
Dependencies are inferred from the claim text.