Multi-die stacked power delivery
AssigneeAdvanced Micro Devices, Inc.
InventorsEric J. Chapman, Alan D. Smith, Edward Chang
Life of this patent
Estimating the term…
Abstract
A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.
Claims17
A processor, comprising:
- a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies stacked on top of the first base IC die, a different power domain to each of the first plurality of compute dies, each of the different power domains corresponding to a different power plane,
- wherein the first base IC die is configured to unify power domains of two or more voltage regulator networks of a plurality of voltage regulator networks to provide a first independent power plane to a first compute die of the first plurality of compute dies.
A system, comprising:
- a processor multi-chip module communicably coupled to a host processor, wherein the processor multi-chip module includes:
- a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a different power domain to each of the first plurality of compute dies, each of the different power domains corresponding to a different power plane,
- wherein the first base IC dies is configured to unify power domains of two or more voltage regulator networks of a plurality of voltage regulator networks to provide a first independent power plane to a first compute die of the first plurality of compute dies.
An integrated circuit device, comprising:
- a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies, each unique power domain corresponding to a different power plane,
- wherein the first base IC die is configured to unify power domains of two or more voltage regulator networks of a plurality of voltage regulator networks to provide a first independent power plane to a first compute die of the first plurality of compute dies.
Dependencies are inferred from the claim text.