US 11,960,338 B2Granted

Activity smoothener circuit controlling rates of change of localized processing activity in an integrated circuit (IC), and related methods

AssigneeMicrosoft Technology Licensing, LLC

InventorsSmitha L. Rapaka, Derek E. Gladding, Xiaoling Xu

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Abstract

An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

Claims24

Dependent claims

An activity smoothener circuit in an integrated circuit (IC), the activity smoothener circuit comprising:

a plurality of circuit blocks (tiles) each comprising an execution circuit, each of the plurality of tiles configured to:
generate a first indication of desired activity of the tile, comprising a single-bit signal indicating a request for one of inactivity and activity in the execution circuit;
receive a first indication of actual activity for the tile, comprising a multi-bit signal representing an allowed level of activity;
and
control task execution activity in the execution circuit of the tile according to the allowed level of activity indicated by the received first indication of actual activity for the tile;
a plurality of smoothening circuits, each corresponding to a cluster of the plurality of tiles, each of the plurality of smoothening circuits configured to:
receive the first indications of desired activity from each of the plurality of tiles;
generate a second indication of desired activity for the cluster, comprising a multi-bit signal indicating a requested level of activity in the cluster based on the first indications of desired activity in the plurality of tiles;
receive a second indication of actual activity for the cluster as a multi-bit signal representing an allowed level of activity for the cluster;
and
generate the first indications of actual activity for each of the plurality of tiles based on the first indications of desired activity in the plurality of tiles, the second indication of actual activity in the cluster, and a first limit of a rate of change of current in each of the plurality of tiles of the IC;
and
a top-level smoothening circuit coupled to the plurality of smoothening circuits, the top-level smoothening circuit configured to:
receive the second indications of desired activity from the plurality of clusters;
generate a third indication of desired activity for the IC based on the second indications of desired activity of the clusters, the third indication of desired activity comprising a multi-bit signal;
receive a third indication of actual activity for the IC comprising a multi-bit signal indicating a level of activity in the IC;
and
generate the second indications of actual activity for the plurality of clusters based on the second indications of desired activity, the third indication of actual activity in the IC, and a second limit of a rate of change of current into the IC.

15 more elements

An integrated circuit (IC) comprising an activity smoothener circuit comprising:

a plurality of cluster smoothening circuits each corresponding to a cluster and each configured to:
receive a plurality of first indications of desired activity for each of a plurality of circuit blocks (tiles) that each comprise an execution circuit, wherein a first indication is generated in each of the tiles indicting a request for one of inactivity and activity in the execution circuit;
generate a second indication of desired activity for the cluster comprising a multi-bit signal indicating a requested level of activity in the cluster based on the plurality of first indications of desired activity;
receive a second indication of actual activity for the cluster as a multi-bit signal representing an allowed level of activity;
and
generate a first indication of actual activity for each of the plurality of tiles based on the plurality of first indications of desired activity in the plurality of tiles, the second indication of actual activity in the cluster, and a first limit of a rate of change of current in each of the plurality of tiles;
and
a node smoothening circuit configured to:
receive from each of the plurality of cluster smoothening circuits, the second indication of desired activity;
generate a third indication of desired activity for the IC based on the second indications of desired activity from the plurality of cluster smoothening circuits, the third indication of desired activity comprising a multi-bit signal;
receive a third indication of actual activity for the IC comprising a multi-bit signal indicating a level of activity in the IC;
and
for each of the plurality of cluster smoothening circuits, generate the second indication of actual activity based on the second indications of desired activity, the third indication of actual activity in the IC, and a second limit of a rate of change of current into the IC.

10 more elements

A method of smoothening activity in an integrated circuit (IC), the method comprising:

in each of a plurality of circuit blocks (tiles) that each comprise an execution circuit, generating a first indication of desired activity of the tile, comprising a single-bit signal indicating a request for one of inactivity and activity in the execution circuit;
receiving a first indication of actual activity for the tile, comprising a multi-bit signal representing an allowed level of activity;
controlling task execution activity in the execution circuit of the tile according to the allowed level of activity indicated by the received first indication of actual activity for the tile;
and
in a plurality of smoothening circuits, each corresponding to a cluster of the plurality of tiles, each of the plurality of smoothening circuits:
receiving the first indications of desired activity from each of the plurality of tiles;
generating a second indication of desired activity for the cluster, comprising a multi-bit signal indicating a requested level of activity in the cluster based on the first indications of desired activity in the plurality of tiles;
receiving a second indication of actual activity for the cluster as a multi-bit signal representing an allowed level of activity for the cluster;
and
generating the first indications of actual activity for each of the plurality of tiles based on the first indications of desired activity in the plurality of tiles, the second indication of actual activity in the cluster, and a first limit of a rate of change of current in each of the plurality of tiles of the IC;
and
in a top-level smoothening circuit coupled to the plurality of smoothening circuits, the top-level smoothening circuit:
receiving the second indications of desired activity from the plurality of clusters;
generating a third indication of desired activity for the IC based on the second indications of desired activity of the clusters, the third indication of desired activity comprising a multi-bit signal;
receiving a third indication of actual activity for the IC comprising a multi-bit signal indicating a level of activity in the IC;
and
generating the second indications of actual activity for the plurality of clusters based on the second indications of desired activity, the third indication of actual activity in the IC, and a second limit of a rate of change of current into the IC.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/182,982Filed 23 Feb 2021
Published: US 2022/0269298 A125 Aug 2022
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 1/28
Power supply means, e.g. regulation thereof: supervision thereof, e.g. detecting power-supply failure by out of limits supervision
G06F 1/305
Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations: in the event of power-supply fluctuations
G06F 9/4893
Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues: taking into account power or heat criteria
G06F 1/329
Power saving characterised by the action undertaken: by task scheduling