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US 11,960,319 B2Granted
Memory device with real-time monitoring
AssigneeSamsung Electronics Co., Ltd.
InventorsTae Min Choi, Chan Ho Lee, Jung Hak Song, Ju Chang Lee, Woo Jin Jung
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Abstract
A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.
Claims18
A memory device comprising:
- an internal clock generator configured to generate an internal clock signal based on an external clock signal received from a host and responsive to a chip enable signal;
- an internal enable signal generator configured to operate based on the internal clock signal, and configured to generate an internal enable signal based on an external enable signal received from the host;
- and
- a monitoring signal generator configured to generate a monitoring signal that indicates whether the memory device is operating under control of the host based on at least one of the internal clock signal or the internal enable signal, and configured to output the monitoring signal from the memory device,
- wherein a comparison of the monitoring signal with the external enable signal indicates, in real time, whether the internal enable signal was generated in accordance with an order in which the external enable signal was received from the host.
2 more elements
An electronic device comprising:
- a host configured to output an external clock signal, a chip enable signal, and at least one external enable signal;
- a memory device configured to operate responsive to the external clock signal and the chip enable signal, and configured to generate an internal enable signal based on the at least one external enable signal, wherein the memory device is configured to generate and output a monitoring signal that indicates whether the memory device is operating under control of the host,
- wherein the memory device comprises a plurality of flip-flop circuits that are electrically connected in a daisy chain configuration, and wherein each of the flip-flop circuits is configured to receive an internal clock signal or the internal enable signal,
- wherein an initial flip-flop circuit of the daisy chain configuration is configured to output a first logic signal to a next flip-flop circuit of the daisy chain configuration in accordance with the internal clock signal, and
- a final flip-flop circuit of the daisy chain configuration is configured to output an output of a previous flip-flop circuit of the daisy chain configuration as the monitoring signal in accordance with the internal enable signal.
2 more elements
An automotive device comprising:
- an automotive processor configured to output a target address, data, an external clock signal, a chip enable signal, and at least one external enable signal;
- and
- a processor embedded memory configured to operate responsive to the external clock signal and the chip enable signal, generate an internal enable signal based on the at least one external enable signal, and perform a data access operation based on the target address,
- wherein the processor embedded memory is configured to generate and output a monitoring signal comprising a real-time operating status responsive to the chip enable signal and the at least one external enable signal, and
- wherein the processor embedded memory comprises a plurality of flip-flop circuits that are electrically connected in a daisy chain configuration, each of the flip-flop circuits is configured to receive an internal clock signal or the internal enable signal, an initial flip-flop circuit of the daisy chain configuration is configured to output a first logic signal to a next flip-flop circuit of the daisy chain configuration in accordance with the internal clock signal, and a final flip-flop circuit of the daisy chain configuration is configured to output an output of a previous flip-flop circuit of the daisy chain configuration as the monitoring signal in accordance with the internal enable signal.
2 more elements
Dependencies are inferred from the claim text.