SPAD based indirect time of flight sensing from solid state transmitter scanning
AssigneeSTMicroelectronics (Grenoble 2) SAS
InventorPascal Mellot
Life of this patent
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Abstract
Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.
Claims17
A time of flight ranging system, comprising:
- an array of single photon avalanche diode (SPAD) pixels;
- and
- control circuitry configured to, during different target illuminations, simultaneously accumulate integrated SPAD event data from a first cluster of SPAD pixels while integrating SPAD event data from a second cluster of SPAD pixels, and then simultaneously accumulate integrated SPAD event data from the second cluster of SPAD pixels while integrating SPAD event data from the first cluster of SPAD pixels.
A method for operating a time of flight ranging system, comprising:
- a) integrating event data from a first single photon avalanche diode (SPAD) cluster during a first target illumination;
- b) integrating event data from a second SPAD cluster during a second target illumination;
- and
- at a start of b), accumulating event data that was integrated during a).
A method for time-of-flight sensing, comprising:
- selectively driving each of VCSEL cluster of a plurality thereof at a predetermined frequency using a VCSEL driver generating a VCSEL drive pulse;
- controlling activation of the VCSEL clusters and a corresponding plurality of SPAD clusters using a sequencer;
- generating first, second, third, and fourth clock signals using a timing generator, wherein the first clock signal is in phase with the VCSEL drive pulse, wherein the third clock signal is an inverse of the first clock signal, wherein the second clock signal is delayed in phase compared to the first clock signal by one quarter of a period, and the fourth clock signal is an inverse of the second clock signal;
- selectively routing output from an OR gate, which combines outputs from quench and readout circuitries associated with the SPAD clusters, to specific counters associated with the SPAD clusters using combination and gating circuitry based on windows of time created by the first, second, third, and fourth clock signals;
- accumulating output of the counters for each SPAD cluster in a memory;
- and
- causing repeated integrations and accumulations of SPAD events between pairs of associated SPAD clusters and VCSEL clusters at a desired number of frequencies using the sequencer.
Dependencies are inferred from the claim text.