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US 11,959,965 B2Granted
Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsGiha Nam, Sangsoon Im
Life of this patent
Estimating the term…
Abstract
Disclosed is a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit may not only transmit a cell function input to a cell function output using only one multiplexer in a bypass mode, may but also use a clock gating scheme capable of blocking a clock signal from transmitting to a scan flip-flop to hold a capture procedure.
Claims19
A test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core, the test circuit comprising:
- a bypass terminal configured to receive a bypass signal;
- a cell function input (CFI) terminal configured to receive a CFI signal from the integrated circuit core or the external circuit;
- a cell function output (CFO) terminal configured to transmit a CFO signal to the integrated circuit core or the external circuit;
- a first multiplexer including a first selection terminal connected to the bypass terminal, a first input terminal connected to the CFI terminal, a second input terminal, and a first output terminal connected to the CFO terminal, and the first multiplexer configured to transmit the CFI signal to the integrated circuit core or the external circuit through the first output terminal as the CFO signal in response to the bypass signal;
- a scan flip-flop;
- a second multiplexer including a second selection terminal connected to a safe mode terminal configured to receive a safe mode signal, a third input terminal connected to an output terminal of the scan flip-flop, a fourth input terminal connected to a safe value terminal configured to receive a safe value signal, and a second output terminal connected to the second input terminal of the first multiplexer, and
- a cell test output (CTO) terminal connected to the output terminal of the scan flip-flop.
4 more elements
A test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core, the test circuit comprising:
- a clock gating circuit configured to:
- receive a scan enable signal through a scan enable terminal, a clock signal through a clock signal terminal and a test signal, and
- output a first output signal to control whether the clock signal is gated in response to a combination of the scan enable signal and the test signal;
- a cell function input (CFI) terminal configured to receive a CFI signal;
- a cell test input (CTI) terminal configured to receive a CTI signal;
- and
- a scan flip-flop configured to:
- receive the first output signal, the CFI signal, and the CTI signal, and
- either hold or output data of captured one of the CFI signal input through the CFI terminal and the CTI signal input through the CTI terminal in response to the first output signal of the clock gating circuit.
6 more elements
An integrated circuit comprising:
- an integrated circuit core;
- and
- a test circuit configured to test the integrated circuit core or an external circuit of the integrated circuit core, and the test circuit including:
- an input cell configured to transmit a first signal to the integrated circuit core, and the input cell including:
- a first scan flip-flop;
- a first bypass terminal configured to receive a bypass signal;
- a first cell function input (CFI) terminal configured to receive a CFI signal from the external circuit;
- a first cell function output (CFO) terminal configured to transmit the first signal to the integrated circuit core;
- and
- a first multiplexer including a first selection terminal connected to the first bypass terminal, a first input terminal connected to the first CFI terminal, a second input terminal, and a first output terminal connected to the first CFO terminal, and the first multiplexer configured to transmit the CFI signal to the integrated circuit core through the first output terminal as the first signal in response to the bypass signal;
- a second multiplexer including a second selection terminal connected to a safe mode terminal configured to receive a safe mode terminal, a third input terminal connected to an output terminal of the first scan flip-flop, a fourth input terminal connected to a safe value terminal configured to receive a safe value signal, and a second output terminal connected to the second input terminal of the first multiplexer;
- and
- a cell test output (CTO) terminal connected to the output terminal of the first scan flip-flop.
10 more elements
Dependencies are inferred from the claim text.