Voltage tracking circuit and method of operating the same

A voltage tracking circuit, comprising:

• a control logic circuit;
• a first transistor in a first well, the first transistor including a first body terminal, a first gate terminal, a first drain terminal and a first source terminal, the first source terminal being coupled to a first voltage supply, the first gate terminal being coupled to the control logic circuit and configured to receive a control logic signal, the first body terminal being coupled to the first voltage supply;
• a second transistor in a second well different from the first well, and being separated from the first well in a first direction, the second transistor including a second body terminal, a second gate terminal, a second drain terminal and a second source terminal, the second source terminal being coupled to the first drain terminal, the second gate terminal being coupled to the first gate terminal and the control logic circuit, and configured to receive the control logic signal, and the second body terminal being coupled to at least a first node;
• a third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to the first voltage supply;
• and
• a fourth transistor including a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the fourth drain terminal being coupled to the third source terminal, the fourth gate terminal being coupled to the third gate terminal and the first voltage supply, and the fourth source terminal being coupled to a pad voltage terminal.

A method of operating a pad voltage tracking circuit, comprising:

• receiving a pad voltage on a pad voltage terminal, the pad voltage being less than a supply voltage of a first voltage supply;
• turning off at least a first set of transistors coupled to the pad voltage terminal, and turning on a second set of transistors coupled to the first voltage supply, a first transistor of the first set of transistors being in a first well, and a second transistor of the second set of transistors being in a second well different from the first well, wherein turning off at least the first set of transistors comprises:
• electrically decoupling a first node from the pad voltage terminal by the first set of transistors;
• and
• electrically coupling the first node with the first voltage supply by the second set of transistors.