US 11,959,956 B2Granted

Circuit check method and electronic apparatus

AssigneeRealtek Semiconductor Corp.

InventorsYun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao

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Abstract

A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Claims8

Dependent claims

A circuit check method, applicable to a to-be-tested circuit, wherein the to-be-tested circuit comprises at least one first node related to a gate voltage of at least one transistor device and a plurality of second nodes, and the circuit check method comprises:

setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit;
obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device, wherein the first node voltage comprises a first maximum value and a first minimum value of the first node;
obtaining a second node voltage of each second node through analysis according to the conduction path, the endpoint voltages, and the first node voltage;
and
performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage;
wherein the transistor device is one of an N-type MOS (NMOS) device or a P-type MOS (PMOS) device;
wherein when the transistor device is the N-type MOS (NMOS) device and in response to the NMOS device being turned on, a source voltage maximum value of the NMOS device is a smaller one in a gate voltage maximum value and a drain voltage maximum value of the NMOS device, and is taken as the first maximum value;
and a drain voltage minimum value of the NMOS device is a source voltage minimum value, and is taken as the first minimum value;
and
wherein when the transistor device is the P-type MOS (PMOS) device and in response to the PMOS device being turned on, a drain voltage maximum value of the PMOS device is a source voltage maximum value, and is taken as the first maximum value;
and a source voltage minimum value of the PMOS device is a larger one in a gate voltage minimum value and a drain voltage minimum value of the PMOS device, and is taken as the first minimum value.

8 more elements

An electronic apparatus, configured to check a to-be-tested circuit, wherein the to-be-tested circuit comprises at least one first node related to a gate voltage of at least one transistor device and a plurality of second nodes, the electronic apparatus performs a circuit check method on the to-be-tested circuit, and the circuit check method comprises:

setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit;
obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device, wherein the first node voltage comprises a first maximum value and a first minimum value of the first node;
obtaining a second node voltage of each second node through analysis according to the conduction path, the endpoint voltages, and the first node voltage;
and
performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage;
wherein the transistor device is a metal oxide semiconductor (MOS) device, and the MOS device is an N-type MOS (NMOS) device, a P-type MOS (PMOS) device, or any combination of the NMOS device and the PMOS device;
wherein when the MOS device is the NMOS device and is turned on, a source voltage maximum value of the NMOS device is a smaller one in a difference between a gate voltage maximum value and a threshold voltage and a drain voltage maximum value of the NMOS device, and is taken as the first maximum value;
and a drain voltage minimum value of the NMOS device is a source voltage minimum value, and is taken as the first minimum value;
and
when the MOS device is the PMOS device and is turned on, a drain voltage maximum value of the PMOS device is a source voltage maximum value, and is taken as the first maximum value;
and a source voltage minimum value of the PMOS device is a larger one in a difference between a gate voltage minimum value and a threshold voltage and a drain voltage minimum value of the PMOS device, and is taken as the first minimum value.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/125,034Filed 17 Dec 2020
Priority: TW 10814653218 Dec 2019
Published: US 2021/0190844 A124 Jun 2021
Granted: 16 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G01R 31/002
Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing: where the device…
G01R 31/2839
Fault-finding or characterising: using signal generators, power supplies or circuit analysers
G01R
Measuring electric variables