Semiconductor memory device and structure
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Jin-Woo Han
Life of this patent
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Abstract
A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.
Claims7
A 3D memory device, the device comprising:
- a first level comprising first memory cells, each of said first memory cells comprising a first transistor;
- a second level comprising second memory cells, each of said second memory cells comprising a second transistor,
- wherein said second level is disposed above said first level,
- wherein a plurality of said first memory cells comprise a shared first source line and a shared first drain line,
- wherein a plurality of said second memory cells comprise a shared second source line and a shared second drain line, and
- wherein at least one of said first memory cells is self-aligned to at least one of said second memory cells;
- and
- a third level comprising memory control circuits,
- wherein said third level is bonded above said second level,
- wherein said plurality of said second memory cells comprise channel regions disposed in-between said shared second source line and said shared second drain line,
- wherein said channel regions are controlled by right side gate lines and left side gate lines,
- wherein said device further comprises:
- a plurality of horizontal word lines above said second layer,
- wherein said horizontal word lines comprise odd word lines and even word lines, and
- wherein said odd word lines are connected to said right side gate lines, and
- wherein said even word lines are connected to said left side gate lines.
A 3D memory device, the device comprising:
- a first memory layer comprising a plurality of first vertical memory cells,
- a second memory layer comprising a plurality of second vertical memory cells,
- wherein said second memory layer is disposed above said first memory layer,
- wherein said plurality of first vertical memory cells comprise a horizontal shared first source line and a horizontal shared first drain line,
- wherein said plurality of second vertical memory cells comprise a horizontal shared second source line and a horizontal shared second drain line,
- wherein at least one of said first vertical memory cells is self-aligned to at least one of said second vertical memory cells, being processed following a same lithography step;
- a staircase structure with contacts to said horizontal shared first source line,
- wherein said horizontal shared first source line comprises said contacts on both ends of said horizontal shared source first line;
- and
- a vertically-oriented, interdigitated word-line comb wrapped around said first and second vertical memory cells.
Dependencies are inferred from the claim text.