Back to results
US 11,956,940 B2Granted
Vertical heterostructure semiconductor memory cell and methods for making the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGerben Doornbos, Marcus Johannes Henricus Van Dal
Life of this patent
Estimating the term…
Abstract
A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.
Claims20
A memory cell, comprising:
- a transistor, comprising:
- a source region;
- a drain region;
- a channel region stacked between the source region and the drain region in a first direction;
- and
- a gate structure adjacent the channel region and extending lengthwise in a second direction perpendicular to the first direction;
- and
- a capacitive device, comprising:
- a first conductor extending above the transistor in the first direction;
- a dielectric material on the first conductor;
- and
- a second conductor on a side of the dielectric material opposite the first conductor, and extending lengthwise in a third direction perpendicular to the first direction and the second direction.
9 more elements
A memory device, comprising:
- a pair of bit lines;
- a plurality of transistors stacked between the pair of bit lines in a first direction, wherein each transistor of the plurality of transistors comprises:
- a source region;
- a drain region;
- a channel region stacked between the source region and the drain region in the first direction;
- and
- a gate structure adjacent the channel region and extending lengthwise in a second direction perpendicular to the first direction;
- and
- a capacitive device stacked between the plurality of transistors in the first direction, wherein the capacitive device comprises:
- a first conductor extending between the plurality of transistors in the first direction;
- a dielectric material on the first conductor;
- and
- a second conductor on a side of the dielectric material opposite the first conductor, and extending lengthwise in a third direction perpendicular to the first direction and the second direction.
10 more elements
A method of forming a memory cell, comprising:
- forming a source region, a drain region, and a channel region of a transistor, wherein the source region, the drain region and the channel region are stacked in a first direction;
- forming a gate structure of the transistor adjacent the channel region and extending lengthwise in a second direction perpendicular to the first direction;
- forming a first conductor of a capacitive device, wherein the first conductor is stacked on the transistor and extends above the transistor in the first direction;
- forming a dielectric material of the capacitive device on the first conductor;
- and
- forming a second conductor of the capacitive device on a side of the dielectric material opposite the first conductor, wherein the second conductor extends lengthwise in a third direction perpendicular to the first direction and the second direction.
3 more elements
Dependencies are inferred from the claim text.