Low-capacitance feedforward level-translator architecture for high-speed multi-phase oscillators
AssigneeAnalog Devices, Inc.
InventorsEric A. Sagen, Dheemanth Prabhu Hejamady
Life of this patent
Estimating the term…
Abstract
This disclosure relates to multi-phase oscillators for electronic systems. An example system includes multiple level translator circuits and a ring oscillator circuit that includes multiple outputs. Each level translator circuit includes a first input transistor, a second input transistor, and an output. The ring oscillator circuit includes multiple outputs, and each output of the ring oscillator has a different phase. An output of the ring oscillator is coupled to only one input transistor of a level translator circuit, and the other input transistor of the level translator circuit is coupled to an output of another level translator circuit.
Claims18
A multi-phase oscillator circuit, the circuit comprising:
- multiple level translator circuits, each level translator circuit including a first input transistor, a second input transistor, and an output;
- a ring oscillator circuit including multiple stages, a control voltage input, and multiple outputs, wherein each output of the ring oscillator has a different phase;
- wherein the control voltage input is a first circuit supply for the multiple stages of the ring oscillator circuit;
- and
- wherein an output of the ring oscillator is only coupled to one input transistor of a level translator circuit, and the other input transistor of the level translator circuit is coupled to an output of another level translator circuit and the level translator circuit is connected to a second circuit supply rail.
A phase lock loop (PLL) circuit, the PLL circuit comprising:
- an input to receive a reference oscillator signal and an output to provide an output clock signal;
- a feedback loop that corrects phase error between the output clock signal and the reference oscillator signal;
- and
- a multi-phase oscillator circuit to generate the output clock signal, the multi-phase oscillator circuit including:
- a ring oscillator circuit including multiple inverters connected in series in a ring, wherein a circuit supply of the inverters is a control voltage;
- multiple level translator circuits, each level translator circuit including a first input transistor, a second input transistor, an output, and a connection to a circuit supply different from the circuit supply of the inverters;
- and
- wherein an output of an inverter of the ring oscillator circuit is coupled to the next inverter of the ring oscillator circuit and to only one input transistor of a level translator circuit, and the other input transistor of the level translator circuit is coupled to an output of another level translator circuit.
A method of generating a level translated clock signal, the method comprising:
- generating multiple phase output signals using a ring oscillator circuit;
- generating the level translated clock signal using a first level translator circuit by driving a first input transistor of the first level translator circuit using a phase output of the ring oscillator, and driving a second input transistor of the first level translator circuit using a previous phase output of the ring oscillator passed through another level translator circuit;
- receiving a first voltage level from a phase detector circuit;
- and
- adjusting the first voltage level to reducing an error between the generated level translated clock signal and a reference clock signal.
Dependencies are inferred from the claim text.