US 11,955,530 B2Granted

RF MOS varactor

AssigneeTexas Instruments Incorporated

InventorsJeff Archimedes Babcock, Will David French, Dahlstrom Erik Mattias

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Abstract

An integrated circuit includes a substrate having a first conductivity type. A well formed at an upper surface has a second, opposite conductivity type and a first dopant concentration. First and second STI structures are formed and a polysilicon gate structure is formed between the first and second STI structures. The polysilicon gate structure extends over a first side of the first STI structure and over a first side of the second STI structure. A first doped region is formed within the well at the upper surface and on a second side of the first STI structure and a second doped region is formed within the well at the upper surface and on a second side of the second STI structure. The first and second doped regions each have the second conductivity type and a second dopant concentration that is greater than the first dopant concentration.

Claims22

Dependent claims

A method of fabricating an integrated circuit comprising:

forming shallow trench isolation (STI) structures at a surface of a substrate, the substrate having a first conductivity type, the STI structures including a first STI structure and a second STI structure;
forming a well at the substrate surface, the well surrounding the STI structures, the well having an opposite second conductivity type and a first dopant concentration;
forming a first polysilicon gate structure over the well, a first portion of the first polysilicon gate structure extending over a first side of the first STI structure and a second portion of the first polysilicon gate structure extending over a first side of the second STI structure;
and
forming contact regions at the substrate surface and within the well, the contact regions having a second dopant concentration that is greater than the first dopant concentration, the contact regions including a first contact region and a second contact region, the first contact region on an opposite second side of the first STI structure and the second contact region on an opposite second side of the second STI structure.

2 more elements

An integrated circuit comprising:

a substrate having a first conductivity type, the substrate having an upper surface;
a well formed at the upper surface, the well having a second conductivity type that is opposite the first conductivity type, the well having a first dopant concentration;
a first shallow trench isolation (STI) structure formed at the upper surface and within the well;
a second STI structure formed at the upper surface and within the well;
a first polysilicon gate structure formed over the upper surface between the first STI structure and the second STI structure, a first portion of the first polysilicon gate structure extending over a first side of the first STI structure and a second portion of the first polysilicon gate structure extending over a first side of the second STI structure;
a first doped region formed within the well at the upper surface and on a second side of the first STI structure;
and
a second doped region formed within the well at the upper surface and on a second side of the second STI structure, the first and second doped regions each having the second conductivity type and a second dopant concentration that is greater than the first dopant concentration.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/514,532Filed 29 Oct 2021
Published: US 2023/0135765 A14 May 2023
Granted: 9 Apr 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 1/048
Of conductor-insulator-semiconductor capacitors, e.g. trench capacitors: having PN junctions, e.g. hybrid capacitors with MOS control
H10D 1/64
Capacitors having potential barriers: variable-capacitance diodes, e.g. varactors
H10D 1/66
Capacitors having potential barriers: conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions