Method and system for optimizing data transfer from one memory to another memory
AssigneeNordic Semiconductor ASA
InventorChris Smith
Life of this patent
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Abstract
A method and system for moving data from a source memory to a destination memory by a processor are disclosed. The processor has a plurality of registers and the source memory stores a sequence of instructions that include one or more load instructions and one or more store instructions. The processor moves the load instructions from the source memory to the destination memory. Then, the processor initiates execution of the load instructions from the destination memory in order to load the data from the source memory to one or more registers in the processor. Execution then returns to the sequence of instructions stored in the source memory, and the processor stores the data from the registers to the destination memory.
Claims20
A method of moving data from a source memory to a destination memory by a processor comprising a plurality of registers, the source memory storing a sequence of instructions, wherein the sequence of instructions comprises one or more load instructions and one or more store instructions, the method comprising:
- moving the one or more load instructions from the source memory to the destination memory;
- initiating execution of the one or more load instructions from the destination memory;
- loading the data from the source memory to at least one register in the processor, on executing the one or more load instructions;
- returning execution to the sequence of instructions stored in the source memory;
- and
- storing the data from the at least one register to the destination memory on executing the one or more store instructions from the source memory.
A computer system configured for moving data, the system comprising:
- a source memory configured to store a sequence of instructions and the data, wherein the sequence of instructions comprises one or more load instructions and one or more store instructions;
- a destination memory;
- and
- a processor, coupled to the source memory and the destination memory, configured to execute the sequence of instructions, wherein the processor is configured to:
- move the one or more load instructions from the source memory to the destination memory;
- initiate execution of the one or more load instructions from the destination memory;
- load the data from the source memory to at least one register in the processor, on executing the one or more load instructions;
- return execution to the sequence of instructions stored in the source memory;
- and
- store the data from the at least one register to the destination memory on executing the one or more store instructions from the source memory.
Dependencies are inferred from the claim text.