Multi-threading microprocessor with a time counter for statically dispatching instructions

A multithreaded processor comprising:

• a clock circuit;
• a time counter storing a time count representing a current time of the processor, wherein the time count is incremented with each cycle of the clock circuit;
• an instruction issue unit coupled to the time counter for receiving a first instruction of a first thread, and issuing the first instruction with a preset execution time based on the time count;
• an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction of the first thread, and dispatch the first instruction to a functional unit when the time count matches the preset execution time;
• a register scoreboard storing a write time of a selected register from a plurality of registers in a register file, wherein the write time is a future time specified by the time count, wherein the register file includes registers for renaming architectural registers of all thread and temporary registers;
• an instruction decode unit coupled to the register scoreboard in which the instruction decode unit reads write times for source operands of the first instruction from the register scoreboard, and uses the write times to determine an execution time for the first instruction;
• a time-resource matrix coupled to the register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter, and
• wherein the available resources include at least one of:
• a plurality of read buses, a plurality of write buses, and a plurality of functional units.

A method, executed within a processor, for reading a register scoreboard for write times of registers in a register file, the method comprising:

• determining an execution time of a first instruction;
• issuing the first instruction of a first thread to an execution queue in the processor to execute at a future time wherein the future time based on a write time is obtained from the register scoreboard;
• and
• issuing a second instruction of a second thread to an execution queue in a processor to execute at a future time wherein the future time based on a write time is obtained from the register scoreboard;
• wherein the execution time represents a time from a time counter which is incremented with each clock cycle of a clock circuit from a zero count to an Nth-bit count value, which represents a largest future time for issuance of an instruction, the time counter storing a time count representing a current time of the processor, and wherein the N-bit counter returns to the zero count after reaching the Nth-bit count value.