US 11,953,548 B2 · Invisible scan architecture for secure testing of digital designs

Abstract

Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality. Specific sequences of key patterns cause the design to transition into a test mode or a normal mode.

Claims20

Dependent claims

A computer-implemented method comprising:

receiving one or more key patterns for testing a design of a hardware intellectual property (IP), wherein (a) the design comprises one or more invisible scan chains and (b) each invisible scan chain comprises a plurality of flip-flops connected on-demand upon verification of the one or more key patterns;
determining a mode for the design based at least in part on the one or more key patterns and using a scan enable finite state machine (SEFSM);
responsive to determining a test mode for the design:
loading a set of scan input data into the one or more invisible scan chains of the design over a first configurable number of clock cycles;
causing the design to perform a normal operation for a second configurable number of clock cycles;
and
obtaining a set of scan output data from the one or more invisible scan chains of the design over the first configurable number of clock cycles;
and
performing one or more automated actions based at least in part on whether the set of scan output data is in accordance with an expected set of scan output data.

6 more elements

Dependencies are inferred from the claim text.

Invisible scan architecture for secure testing of digital designs

Life of this patent

Invisible scan architecture for secure testing of digital designs

Life of this patent

Abstract

Claims20