Monolithic humidity sensor devices and methods of manufacture
AssigneeTexas Instruments Incorporated
InventorsRicky Alan Jackson, Wai Lee
Life of this patent
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Abstract
Monolithic humidity sensor devices, and methods of manufacture. The devices include circuitry on or over a silicon substrate. A primary passivation barrier is formed over the circuitry with conductive vias therethrough; a capacitor, comprising metal fingers with spaces therebetween, is formed above said primary passivation barrier and electrically coupled by the conductive vias to the circuitry. A secondary passivation barrier is formed over the capacitor. A hygroscopic material layer is formed over the secondary passivation barrier, wherein the capacitor is operable to exhibit a capacitance value responsive to moisture present in the hygroscopic material layer and the circuitry is operable to generate a signal responsive to said capacitance value.
Claims20
A method of forming an integrated circuit, comprising the steps of:
- forming circuitry on or over a silicon substrate, the circuitry including top-level metal interconnects;
- forming a primary passivation barrier over said top-level metal interconnects;
- forming conductive vias through said primary passivation barrier to said top-level metal interconnects;
- forming a capacitor above said primary passivation barrier and electrically coupling said capacitor through said conductive vias to said circuitry, said capacitor comprising interdigitated metal fingers with spaces therebetween;
- forming a secondary passivation barrier over said capacitor;
- and,
- forming a hygroscopic material layer over said secondary passivation barrier, wherein said capacitor is operable to exhibit a capacitance value responsive to moisture present in said hygroscopic material layer and said circuitry is operable to generate a signal responsive to said capacitance value.
An integrated circuit, comprising:
- a silicon substrate;
- circuitry on or over said silicon substrate, the circuitry including top-level metal interconnects;
- a primary passivation barrier over said top-level metal interconnects;
- conductive vias through said primary passivation barrier to said top-level metal interconnects;
- a capacitor above said primary passivation barrier and electrically coupled through said conductive vias to said circuitry, said capacitor comprising interdigitated metal fingers with spaces therebetween;
- a secondary passivation barrier over said capacitor;
- and,
- a hygroscopic material layer over said secondary passivation barrier, wherein said capacitor is operable to exhibit a capacitance value responsive to moisture present in said hygroscopic material layer and said circuitry is operable to generate a signal responsive to said capacitance value.
An integrated circuit, comprising:
- a circuitry layer over a semiconductor substrate, the circuitry layer including metal interconnects;
- a planarized passivation layer over the circuitry layer;
- an interdigitated capacitor over the passivation layer, the interdigitated capacitor including a plurality of metal lines configured as a first capacitor electrode and a second capacitor electrode;
- and
- one or more vertical interconnections that connect at least one of the first and second capacitor electrodes to the circuitry layer through the passivation layer.
Dependencies are inferred from the claim text.