Memory device having 2-transistor vertical memory cell and wrapped data line structure

A method comprising:

• forming a first transistor and a second transistor of a first memory cell, such that the first transistor includes a first channel region, and a first charge storage structure separated from the first channel region by a first dielectric material, and the second transistor includes a second channel region formed over the charge storage structure;
• forming a first additional transistor and a second additional transistor of a second memory cell, such that the first additional transistor includes a first additional channel region, and a second charge storage structure separated from the first additional channel region by a first additional dielectric material, and the second additional transistor includes a second additional channel region formed over the second charge storage structure;
• forming a trench in a second dielectric material adjacent the first channel region and the first additional channel region, such that the trench is separated from each of the first channel region and the first additional channel region by a portion of the second dielectric material;
• forming a conductive line, such that the conductive line is electrically separated from the first and second channel regions and spans across part of the first and second channel regions, and such that the conductive line is electrically separated from the first and second additional channel regions and spans across part of the first and second additional channel regions;
• and
• forming a data line over the first and second channel regions, such that the data line includes a first portion and a second portion, the first portion is in the trench and separated from the channel region by a first portion of the second dielectric material, the second portion is in the trench and separated from the additional channel region by a second portion of the second dielectric material.

A method comprising:

• forming memory cell including:
• forming a first transistor including a first channel region, and a charge storage structure separated from the first channel region;
• and
• forming a second transistor including a second channel region over the charge storage structure;
• and
• forming a first conductive line, such that the first conductive line electrically separated from a first side of the first and second channel regions by a first dielectric material and spanning across part of the first and second channel regions;
• forming a second conductive line, such that the second conductive line is electrically separated from a second side of the first and second channel regions by a second dielectric material and spans across part of the first and second channel regions;
• and
• forming a data line over and contacting the first channel region and the second channel region, such that the data line includes a portion adjacent the first channel region and separated from the first channel region by a portion of a dielectric material.