# US 11,950,356 B2 · Mating backplane for high speed, high density electrical connector > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,950,356 B2 - Document ID: US11950356B2 - Status: Granted - Kind: B2 - Application number: 18/079,956 - Filed: 2022-12-13 - Published: 2023-04-13 - Granted: 2024-04-02 - Earliest claimed: 2014-11-21 - Assignees: Amphenol Corporation - Applicants: Amphenol Corporation - Inventors: Mark W. Gailus; Marc B. Cartier, Jr.; Vysakh Sivarajan; David Levine - Web page: https://patentgrep.com/patent/US11950356B2 ## CPC - H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence} - H01R 43/205: {with a panel or printed circuit board} - H05K 1/0216: {Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215)} - H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors} - H05K 1/025: {Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance (H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H10W44/20)} - H05K 1/0251: {related to vias or transitions between vias and transmission lines} - H05K 1/0253: {Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence)} - H05K 1/0298: {Multilayer circuits} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 3/0047: {Drilling of holes} - H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)} - H05K 3/429: {Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers} - H05K 2201/07: Electric details - H05K 2201/09063: Holes or slots in insulating substrate not used for electrical connections - H05K 2201/09318: Core having one signal plane and one power plane - H05K 2201/09545: Plated through-holes or blind vias without lands - H05K 2201/096: Vertically aligned vias, holes or stacked vias - H05K 2201/097: Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components - H05K 2201/09718: Clearance holes - H05K 2201/09845: Stepped hole, via, edge, bump or conductor - H05K 2201/09854: Hole or via having special cross-section, e.g. elliptical - H05K 2201/10189: Non-printed connector - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS ## Abstract A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns. ## Claims ### Claim 1 A printed circuit board comprising: a plurality of layers including conductive layers separated by dielectric layers; and via patterns formed in one or more of the plurality of layers, each of the via patterns comprising: first and second signal vias connecting to respective signal traces on one or more of the plurality of layers; ground vias extending through at least some layers of the plurality of layers; and at least one shadow via extending through at least some layers of the plurality of layers, wherein the at least one shadow via is plated or filled with a conductive material and wherein the at least one shadow via is located on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias. ### Claim 2 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via is located in proximity to one of the first and second signal vias. ### Claim 3 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via comprises first and second shadow vias located in proximity to the first signal via and third and fourth shadow vias located in proximity to the second signal via. ### Claim 4 (depends on 3) The printed circuit board as defined in claim 3, wherein the first and second shadow vias are located on opposite sides of the first signal via and the third and fourth shadow vias are located on opposite sides of the second signal via. ### Claim 5 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via extends to a predetermined depth in the plurality of layers. ### Claim 6 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via extends through the plurality of layers. ### Claim 7 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via is in electrical contact with one or more of the conductive layers. ### Claim 8 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via is located in proximity to one of the ground vias. ### Claim 9 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via is smaller in diameter than the first and second signal vias. ### Claim 10 (depends on 1) The printed circuit board as defined in claim 1, wherein the at least one shadow via is smaller in diameter than the ground vias. ### Claim 11 A printed circuit board comprising: a plurality of layers including conductive layers separated by dielectric layers; first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers; and at least one shadow via parallel to and spaced apart from one of the first and second signal vias, wherein the at least one shadow via is plated or filled with a conductive material, wherein at least one of the conductive layers of the plurality of layers is removed in an area around the first and second signal vias to form an antipad, and wherein the at least one shadow via is located, at least partially, within the antipad. ### Claim 12 (depends on 11) The printed circuit board as defined in claim 11, wherein the at least one shadow via includes shadow vias located on opposite sides of the first and second signal vias. ### Claim 13 (depends on 11) The printed circuit board as defined in claim 11, wherein the at least one shadow via has a smaller diameter than the first and second signal vias. ### Claim 14 (depends on 11) The printed circuit board as defined in claim 11, wherein the at least one shadow via comprises first and second shadow vias located in proximity to the first signal via and third and fourth shadow vias located in proximity to the second signal via. ### Claim 15 (depends on 11) The printed circuit board as defined in claim 11, wherein the at least one shadow via is in electrical contact with one or more of the conductive layers. ### Claim 16 A printed circuit board comprising: a plurality of layers including conductive layers separated by dielectric layers; and a connector footprint comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through one or more of the plurality of layers; and at least one shadow via associated with one of the first and second signal vias and extending to a predetermined depth in the plurality of layers, wherein the at least one shadow via is located on a first line that passes through one of the first and second signal vias, the first line being perpendicular to a second line that passes through the first and second signal vias. ### Claim 17 (depends on 16) The printed circuit board as defined in claim 16, wherein the at least one shadow via comprises first and second shadow vias located in proximity to the first signal via and third and fourth shadow vias located in proximity to the second signal via. ### Claim 18 (depends on 16) The printed circuit board as defined in claim 16, wherein the at least one shadow via is smaller in diameter than the first and second signal vias.