US 11,949,419 B2 · Delay adjustment circuits

Abstract

Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

Claims20

Dependent claims

An apparatus, comprising:

a set of signal lines;
and
a circuit configured to provide a load on the set of signal lines associated with a set of signals of a multi-phase clock, the circuit comprising:
a set of amplifiers each having a respective input coupled with a corresponding signal line of the set of signal lines, the set of amplifiers having respective gains at nodes of the set of amplifiers relative to the respective inputs;
a sub-circuit coupled with the set of amplifiers and configured to control the respective gains of the set of amplifiers;
and
a second circuit having a set of inputs coupled with the set of signal lines, the second circuit coupled with the sub-circuit and configured to control the sub-circuit based on signals detected on the set of inputs.

4 more elements

A memory system, comprising:

one or more memory devices;
and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
couple a set of signal lines associated with a set of signals to an input side of a set of buffers;
obtain a set of delayed signals on the set of signal lines based at least in part on coupling the set of signal lines to the set of buffers;
derive a set of clock signals from the set of delayed signals;
obtain a first integration signal for a first clock signal of the set of clock signals based at least in part on a first capacitance and a first resistance;
obtain a second integration signal for a second clock signal of the set of clock signals based at least in part on a second capacitance and a second resistance;
input the first integration signal to a first input of an amplifier and the second integration signal to a second input of the amplifier;
and
bias, by an output of the amplifier, a control line of a transistor.

8 more elements

Dependencies are inferred from the claim text.

Delay adjustment circuits

Life of this patent

Delay adjustment circuits

Life of this patent

Abstract

Claims20