Polyphase filter control scheme for fractional resampler systems
AssigneeXilinx, Inc.
InventorsRhona Wade, John Edward McGrath
Life of this patent
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Abstract
Embodiments herein describe a hardened fractional resampler that includes a fixed filter that supports simultaneous processing of N input samples with minimal additional combinational logic and no additional multipliers. In one embodiment, the fractional resampler is implemented in an integrated circuit using hardened circuit. The embodiments below exploit a pattern in the order filter phases in fractional resampling systems (such as a SSR resampling system) to use filter phases in a single fixed filter to process multiple input samples in parallel, where these filter phases would have been unused in previous resampling systems.
Claims19
A fractional resampling circuit, comprising:
- a fixed coefficient filter comprising a plurality of filter phases, wherein a first filter phase, of the plurality of filter phases, comprises a first plurality of filter taps configured to receive a first same input sample from a plurality of input samples in parallel, and a second filter phase, of the plurality of filter phases, comprises a second plurality of filter taps configured to receive a second same input sample from the plurality of input samples in parallel;
- and
- a delay line configured to provide the plurality of input samples to the plurality of filter phases such that the plurality of filter phases processes the plurality of input samples in parallel according to a resampling ratio, and generate a plurality of output samples in a same clock cycle.
A fractional resampling circuit, comprising:
- a fixed coefficient filter comprising a plurality of filter phases;
- and
- a delay line configured to provide a plurality of input samples to the plurality of filter phases such that the plurality of filter phases processes the plurality of input samples in parallel according to a resampling ratio, and generate a plurality of output samples in a same clock cycle;
- at least one modulo counter configured to increment based on Q mod P where Q is a down sampling value (0) of the resampling ratio and P is the number of the plurality of filter phases;
- and
- a filter phase enable circuit coupled to the output of the at least one modulo counter and configured to output phase enable signals to indicate which of the plurality of filter phases are used to process the plurality of input samples during the same clock cycle.
An integrated circuit, comprising:
- a fixed coefficient filter comprising a plurality of filter phases, wherein a first filter phase, of the plurality of filter phases, comprises a first plurality of filter taps configured to receive a fir same input sample from a plurality of input samples in parallel, and a second filter phase, of the plurality of filter phases, comprises a second plurality of filter taps configured to receive a second same input sample from the plurality of input samples in parallel;
- and
- a delay line configured to provide the plurality of input samples to the plurality of filter phases such that the plurality of filter phases processes the plurality of input samples in parallel according to a resampling ratio, and generate a plurality of output samples in a same clock cycle.
Dependencies are inferred from the claim text.