Silicon on insulator device with partially recessed gate

A method, comprising:

• forming a first doped region and a second doped region by doping an active area of a substrate;
• forming a recess in the active area of the substrate, the recess extending into at least one of the first doped region or the second doped region;
• forming a planar semiconductor layer at least partially in the recess;
• forming a dielectric layer over the planar semiconductor layer;
• forming a conductive layer over the dielectric layer;
• partially recessing the dielectric layer to form an undercut region below the conductive layer;
• and
• encapsulating the conductive layer with a single, continuous encapsulant, the encapsulant filling the undercut region and in contact with an underside of the conductive layer.

A method, comprising:

• forming a mask layer over a substrate;
• forming a recess in the mask layer, the recess exposing an area of the substrate;
• forming a dielectric layer in the recess, the dielectric layer on sidewalls of the recess;
• forming a conductive layer in the recess and over the dielectric layer;
• partially etching the dielectric layer to form an undercut region below the conductive layer;
• removing the mask layer;
• and
• encapsulating the conductive layer with a single, continuous encapsulant, the encapsulant in contact with an underside of the conductive layer in the undercut region.