Memory device
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
InventorsJun-Shen Wu, Chi-En Wang, Ren-Shuo Liu
Life of this patent
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Abstract
A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.
Claims20
A memory device, comprising:
- a memory array, wherein at least one first faulty cell and at least one second faulty cell that are in the memory array are configured to store data corresponding to, respectively, first and second fields of a floating-point number;
- a selection circuit configured to identify the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell, and further configured to determine that an address of the at least one first faulty cell matches one of a plurality of addresses of a group of memory cells to output the address of the at least one first faulty cell as a fault address, wherein the group of memory cells store data corresponding to an exponent field of the floating-point number,
- wherein the selection circuit is further configured to output the fault address to a redundancy analyzer circuit that is configured to perform a replacing operation of replacing the at least one first faulty cell;
- and
- a clipping circuit configured to output the floating-point number read out from the memory array as a read data when the floating-point number is between a first threshold value and a second threshold value smaller than the first threshold value.
A method, comprising:
- testing a memory array to identify a plurality of faulty cells in the memory array;
- identifying in the plurality of faulty cells an excluded cell that meets at least one of a plurality of conditions, wherein the plurality of conditions are associated with a value of a first binary number corresponding to the excluded cell, wherein a first condition of the plurality of conditions indicates that a value of an exponent in the first binary number corresponding to the excluded cell is smaller than an accurate value of the exponent in the first binary number corresponding to the excluded cell;
- replacing at least one cell of remaining cells in the plurality of faulty cells with a redundant cell;
- and
- outputting a second binary number corresponding to the redundant cell as a read data to a neural network processor when the second binary number is between a first threshold value and a second threshold value.
A system, comprising:
- a memory device;
- and
- a neural network processor configured to access the memory device;
- wherein the memory device comprises:
- a plurality of memory cells configured to store a plurality of binary numbers corresponding to data transmitted from/to the neural network processor;
- a selection circuit configured to determine that a first address of a plurality of addresses received from a test circuit matches one of addresses of first memory cells in the plurality of memory cells to output the first address as a fault address, wherein the first memory cells store data corresponding to exponent fields of the plurality of binary numbers, and the plurality of addresses correspond to a plurality of faulty cells,
- wherein the selection circuit is further configured to output the fault address of a first faulty cell in a plurality of faulty cell, wherein the first faulty cell has a first priority in a cell replacement operation and has a stuck-at-1 fault in a bit in the exponent field of a first binary number of the plurality of binary numbers;
- a replacement circuit configured to replace, according to the fault address, the first faulty cell with a redundant cell of a plurality of redundant cells;
- and
- a clipping circuit configured to output to the neural network processor a first threshold value when the first binary number is greater than the first threshold value.
Dependencies are inferred from the claim text.