Non-volatile memory device with vertical state transistor and vertical selection transistor
AssigneeSTMicroelectronics (Rousset) SAS
InventorsQuentin Hubert, Abderrezak Marzaki, Julien Delalleau
Life of this patent
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Abstract
In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.
Claims17
A method for manufacturing a non-volatile memory device, the method comprising:
- forming a trench extending vertically in a semiconductor well of a semiconductor substrate;
- forming a source region at a bottom of the trench;
- forming a gate dielectric layer around sidewalls of the trench;
- forming, in the trench, a selection gate, the gate dielectric layer disposed between the semiconductor well and the selection gate;
- forming a dielectric area on the sidewalls of the trench above the selection gate, the dielectric area comprising two charge trapping dielectric interfaces;
- and
- forming, above the selection gate in the trench, a control gate, the control gate being laterally surrounded by the two charge trapping dielectric interfaces.
A method for manufacturing a non-volatile memory device, the method comprising:
- forming a source plane within a semiconductor substrate;
- forming a semiconductor well over the source plane within the semiconductor substrate;
- forming a trench extending vertically in the semiconductor well of the semiconductor substrate;
- forming a gate dielectric layer disposed on sidewalls of a lower portion of the trench;
- forming a selection gate over the gate dielectric layer in the lower portion of the trench;
- forming a charge trapping dielectric interface proximate the semiconductor well on sidewalls of an upper portion of the trench;
- forming a control gate in the upper portion of the trench, the charge trapping dielectric interface separating the control gate from the semiconductor well;
- and
- forming a drain region proximate the upper portion of the trench, the charge trapping dielectric interface and the control gate forming part of a vertical state transistor configured to trap charges in the charge trapping dielectric interface, and the selection gate and the gate dielectric layer forming part of a vertical selection transistor.
A method for manufacturing a non-volatile memory device, the method comprising:
- forming a semiconductor well isolated from a carrier substrate by an embedded layer and lateral wells having a conductivity type opposite to a conductivity type of the semiconductor well;
- forming trenches in the semiconductor well, the trenches extending into the semiconductor well to the embedded layer;
- forming source regions around a bottom portion of the trenches;
- depositing a gate dielectric layer on sidewalls of the trenches;
- partially filling the trenches with a first conductive material to form select gates in lower portions of the trenches;
- forming a gate isolation area over the first conductive material partially filling the trenches;
- forming dielectric areas along sidewalls of upper portions of the trenches;
- forming a second conductive material over the partially filled trenches;
- and
- planarizing the second conductive material to form control gates.
Dependencies are inferred from the claim text.