Transmitter and receiver for 3-level pulse amplitude modulation signaling and system including the same

A receiver comprising:

• a decoder configured to
• generate a first intermediate bit group by decoding a first symbol group of an input data signal, and generate a second intermediate bit group by decoding a second symbol group of the input data signal, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels, and generate a first bit group and a second bit group by manipulating the first intermediate bit group and the second intermediate bit group differently based on a value of a specific bit of the second intermediate bit group;
• and
• a buffer configured to generate an output data signal including a first number of binary output bits by buffering the first bit group and the second bit group.

A system comprising:

• a transmitter including an encoder and a driver, the transmitter configured to output a write data to be stored in a semiconductor memory device;
• a channel configured to transmit the write data;
• and
• a receiver including a decoder and a buffer, the receiver configured to receive the write data,
• wherein the encoder is configured to
• divide a first number of binary input bits of an input data signal into a first bit group and a second bit group,
• generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and
• generate a first symbol group by encoding the first intermediate bit group and generate a second symbol group by encoding the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels, and
• the driver is configured to generate an output data signal by concatenating the first symbol group and the second symbol group and configured to transmit the output data signal through the channel;
• and
• wherein the decoder is configured to
• receive the output data signal including the first symbol group and the second symbol group,
• generate the first intermediate bit group by decoding the first symbol group and generate the second intermediate bit group by decoding the second symbol group, and
• generate the first bit group and the second bit group by manipulating the first intermediate bit group and the second intermediate bit group differently based on a value of a specific bit of the second intermediate bit group, and
• the buffer is configured to generate an output data signal including the first number of binary output bits by buffering the first bit group and the second bit group.